A clustering based fast clock schedule algorithm for light clock-trees

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E85-A, Issue 12, 2002, Pages 2756-2763

  Saitoh, Makoto ^a   Azuma, Masaaki ^a   Takahashi, Atsushi ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Clock tree; Clock scheduling; Clustering; Semi synchronous circuit

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; ELECTRIC POWER SUPPLIES TO APPARATUS; GRAPH THEORY; NETWORKS (CIRCUITS); SIMULATED ANNEALING;

CLOCK SCHEDULE ALGORITHM; CLOCK TREE; CLOCK-SCHEDULING; CLUSTERING; SEMI-SYNCHRONOUS CIRCUIT;

ALGORITHMS;

EID: 0036999287     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (25)

1. M. Azuma, M. Saitoh, and A. Takahashi, "A clock tree routing algorithm for low power using feasible range of clock schedule," IPSJ SIG Notes, vol.2000, no.79, pp.63-68, 2000.
2. K.D. Boese and A.B. Kahng, "Zero-skew clock routing trees with minimum wirelength," Proc. IEEE 5th ASIC Conf., pp.1.1.1-1.1.5, 1992.
3. T.H. Chao, Y.C. Hsu, and J.M. Ho, "Zero skew clock net routing," Proc. 29th Design Automation Conference (DAC), pp.518-523, 1992.
4. T.H. Chao, Y.C. Hsu, J.M. Ho, K.D. Boese, and A.B. Kahgn, "Zero skew clock routing with minimum wire-length," IEEE Trans. Circuits & Syst., vol.39, no.11, pp.799-814, 1992.
5. Y. Chen, A.B. Kahng, G. Qu, and A. Zelikovsky, "The associative-skew clock routing problem," Proc. International Conference on Computer-Aided-Design (ICCAD), pp.168-172, 1999.
6. J. Cong, A.B. Kahng, C.K. Koh, and C.W.A. Tsao, "Bounded-skew clock and Steiner routing under Elmore delay," Proc. International Conference on Computer-Aided-Design (ICCAD), pp.66-71, 1995.
7. J. Cong and C.K. Koh, "Minimum-cost bounded-skew clock routing," Proc. International Symposium on Circuits and Systems (ISCAS), vol.1, pp.215-218, 1995.
8. R.B. Deokar and S.S. Sapatnekar, "A graph-theoretic approach to clock skew optimization," Proc. International Symposium on Circuits and Systems (ISCAS), vol.1, pp.407-410, 1994.
9. M. Edahiro, "A clustering-based optimization algorithm in zero-skew routings," Proc. 30th Design Automation Conference (DAC), pp.612-616, 1993.
10. M. Edahiro and T. Yoshimura, "Minimum path-length equi-distant routing," Proc. Asia-Pacific Conference on Circuits and Systems (APCCAS), pp.41-46, 1992.
11. J.P. Fishburn, "Clock skew optimization," IEEE Trans. Comput., vol.39, no.7, pp.945-951, 1990.
12. D.J.H. Huang, A.B. Kahng, and C.W.A. Tsao, "On the bounded-skew routing tree problem," Proc. 32nd Design Automation Conference (DAC), pp.508-513, 1995.
13. K. Inoue, W. Takahashi, A. Takahashi, and Y. Kajitani, "Schedule-clock-tree routing for semi-synchronous circuits," IEICE Trans. Fundamentals, vol.E82-A, no.11, pp.2431-2439, Nov. 1999.
14. I.S. Kourtev and E.G. Friedman, "Clock skew scheduling for improved reliability via quadratic programming," Proc. International Conference on Computer-Aided-Design (ICCAD), pp.239-243, 1999.
15. K. Kurokawa, T. Yasui, M. Toyonaga, and A. Takahashi, "A practical clock tree synthesis for semi-synchronous circuits," IEICE Trans. Fundamentals, vol.E84-A, no.11, pp.2705-2713, Nov. 2001.
16. E.L. Lawler, Combinatorial Optimization, Networks and Matroids, Holt, Rinehart and Winston, New York, 1976.
17. X. Liu, M.C. Papaefthymiou, and E.G. Friedman, "Maximizing performance by retiming and clock skew scheduling," Proc. 36th Design Automation Conference (DAC), pp.231-236, 1999.
18. H. Mitsubayashi, A. Takahashi, and Y. Kajitani, "Cost-radius balanced spanning/Steiner trees," IEICE Trans. Fundamentals, vol.E80-A, no.4, pp.689-694, April 1997.
19. M. Saitoh, M. Azuma, and A. Takahashi, "Clustering based fast clock scheduling for light clock-tree," Proc. Design Automation and Test in Europe Conference and Exhibition (DATE), pp.240-244, 2001.
20. A. Takahashi, K. Inoue, and Y. Kajitani, "Clock-tree routing realizing a clock-schedule for semi-synchronous circuits," Proc. International Conference on Computer-Aided-Design (ICCAD), pp.260-265, 1997.
21. A. Takahashi and Y. Kajitani, "Performance and reliability driven clock scheduling of sequential logic circuits," Proc. Asia and South Pacific Design Automation Conference (ASPDAC), pp.37-42, 1997.
22. M. Toyonaga, K. Kurokawa, T. Yasui, and A. Takahashi, "A practical clock tree synthesis for semi-synchronous circuits," Proc. ACM International Symposium on Physical Design (ISPD), pp.159-164, 2000.
23. J.G. Xi and W.W.M. Dai, "Jitter-tolerant clock routing in two-phase synchronous systems," Proc. International Conference on Computer-Aided-Design (ICCAD), pp.316-320, 1996.
24. J.G. Xi and W.W.M. Dai, "Useful-skew clock routing with gate sizing for low power design," Proc. 33rd Design Automation Conference (DAC), pp.383-388, 1996.
25. T. Yoda and A. Takahashi, "Clock schedule design for minimum realization cost," IEICE Trans. Fundamentals, vol.E83-A, no.12, pp.2552-2557, Dec. 2000.