Schedule-clock-tree routing for semi-synchronous circuits

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E82-A, Issue 11, 1999, Pages 2431-2439

  Inoue, Kazunori ^a   Takahashi, Wataru ^a   Takahashi, Atsushi ^a   Kajitani, Yoji ^a  

^a HITACHI LTD   (Japan)

Author keywords

Clock scheduling; Clock tree; Deferred merge embedding; Semi synchronous circuit

Indexed keywords

EID: 0001480667     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (28)

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