-
2
-
-
33747993282
-
Zero-skew clock routing trees with minimum wirelength
-
K. D. Boese and A. B. Kahng. Zero-skew clock routing trees with minimum wirelength. In Proc. IEEE 5th ASIC Conf., pages 1.1.1-1.1.5, 1992.
-
(1992)
Proc. IEEE 5th ASIC Conf.
, pp. 111-115
-
-
Boese, K.D.1
Kahng, A.B.2
-
4
-
-
0026946698
-
Zero skew clock routing with minimum wirelength
-
T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese, and A. B. Kahgn. Zero skew clock routing with minimum wirelength. IEEE Trans, on Circuits and Systems, 39(11):799-814, 1992.
-
(1992)
IEEE Trans, on Circuits and Systems
, vol.39
, Issue.11
, pp. 799-814
-
-
Chao, T.H.1
Hsu, Y.C.2
Ho, J.M.3
Boese, K.D.4
Kahgn, A.B.5
-
5
-
-
0033318397
-
The associative-skew clock routing problem
-
Y. Chen, A. B. Kahng, G. Qu, and A. Zelikovsky. The associative-skew clock routing problem. In Proc. 1999 IC-CAD, pages 168-172, 1999.
-
(1999)
Proc. 1999 IC-CAD
, pp. 168-172
-
-
Chen, Y.1
Kahng, A.B.2
Qu, G.3
Zelikovsky, A.4
-
6
-
-
0029534353
-
Bounded-skew clock and Steiner routing under Elmore delay
-
J. Cong, A. B. Kahng, C. K. Koh, and C. W. A. Tsao. Bounded-skew clock and Steiner routing under Elmore delay. In Proc. 1995 ICCAD, pages 66-71, 1995.
-
(1995)
Proc. 1995 ICCAD
, pp. 66-71
-
-
Cong, J.1
Kahng, A.B.2
Koh, C.K.3
Tsao, C.W.A.4
-
7
-
-
0029204493
-
Minimum-cost bounded-skew clock routing
-
J. Cong and C. K. Koh. Minimum-cost bounded-skew clock routing. In Proc. ISCAS 95, volume 1, pages 215-218, 1995.
-
(1995)
Proc. ISCAS 95
, vol.1
, pp. 215-218
-
-
Cong, J.1
Koh, C.K.2
-
8
-
-
0028571323
-
A graph-theoretic approach to clock skew optimization
-
R. B. Deokar and S. S. Sapatnekar. A graph-theoretic approach to clock skew optimization. In Proc. ISCAS'94, volume 1, pages 407-410, 1994.
-
(1994)
Proc. ISCAS'94
, vol.1
, pp. 407-410
-
-
Deokar, R.B.1
Sapatnekar, S.S.2
-
9
-
-
0027262847
-
A clustering-based optimization algorithm in zero-skew routings
-
M. Edahiro. A clustering-based optimization algorithm in zero-skew routings. In Proc. 30th DAC, pages 612-616, 1993.
-
(1993)
Proc. 30th DAC
, pp. 612-616
-
-
Edahiro, M.1
-
10
-
-
0002266352
-
Minimum path-length equidistant routing
-
M. Edahiro and T. Yoshimura. Minimum path-length equidistant routing. In Proc. APCCAS 92, pages 41-46, 1992.
-
(1992)
Proc. APCCAS 92
, pp. 41-46
-
-
Edahiro, M.1
Yoshimura, T.2
-
11
-
-
0025464163
-
Clock skew optimization
-
J. P. Fishburn. Clock skew optimization. IEEE Trans, on Computers, 39(7):945-951, 1990.
-
(1990)
IEEE Trans, on Computers
, vol.39
, Issue.7
, pp. 945-951
-
-
Fishburn, J.P.1
-
13
-
-
0001480667
-
Schedule-clock-tree routing for semi-synchronous circuits
-
K. Inoue, W. Takahashi, A. Takahashi, and Y Kajitani. Schedule-clock-tree routing for semi-synchronous circuits. IEICE Transactions on Fundamentals, E82-A (11):2431-2439, 1999.
-
(1999)
IEICE Transactions on Fundamentals
, vol.E82-A
, Issue.11
, pp. 2431-2439
-
-
Inoue, K.1
Takahashi, W.2
Takahashi, A.3
Kajitani, Y.4
-
14
-
-
0033308394
-
Clock skew scheduling for improved reliability via quadratic programming
-
I. Kourtev and E. Friedman. Clock skew scheduling for improved reliability via quadratic programming. In Proc. 1999 ICCAD, pages 239-243, 1999.
-
(1999)
Proc. 1999 ICCAD
, pp. 239-243
-
-
Kourtev, I.1
Friedman, E.2
-
16
-
-
0032651059
-
Maximizing performance by retiming and clock skew scheduling
-
X. Liu, M. Papaefthymiou, and E. Friedman. Maximizing performance by retiming and clock skew scheduling. In Proc. 36th DAC, pages 231-236, 1999.
-
(1999)
Proc. 36th DAC
, pp. 231-236
-
-
Liu, X.1
Papaefthymiou, M.2
Friedman, E.3
-
17
-
-
0031117083
-
Cost-radius balanced spanning/Steiner trees
-
H. Mitsubayashi, A. Takahashi, and Y Kajitani. Cost-radius balanced spanning/Steiner trees. IEICE Transactions on Fundamentals, E80-A (4):689-694, 1997.
-
(1997)
IEICE Transactions on Fundamentals
, vol.E80-A
, Issue.4
, pp. 689-694
-
-
Mitsubayashi, H.1
Takahashi, A.2
Kajitani, Y.3
-
18
-
-
0031354140
-
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits
-
A. Takahashi, K. Inoue, and Y Kajitani. Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. In Proc. 1997 ICCAD, pages 260-265, 1997.
-
(1997)
Proc. 1997 ICCAD
, pp. 260-265
-
-
Takahashi, A.1
Inoue, K.2
Kajitani, Y.3
-
19
-
-
0030651638
-
Performance and reliability driven clock scheduling of sequential logic circuits
-
A. Takahashi and Y. Kajitani. Performance and reliability driven clock scheduling of sequential logic circuits. In Proc. ASP-DAC'97, pages 37-42, 1997.
-
(1997)
Proc. ASP-DAC'97
, pp. 37-42
-
-
Takahashi, A.1
Kajitani, Y.2
-
21
-
-
0030381852
-
Jitter-tolerant clock routing in two-phase synchronous systems
-
J. G. Xi and W. W. M. Dai. Jitter-tolerant clock routing in two-phase synchronous systems. In Proc. 1996 ICCAD, pages 316-320, 1996.
-
(1996)
Proc. 1996 ICCAD
, pp. 316-320
-
-
Xi, J.G.1
Dai, W.W.M.2
-
22
-
-
0029722521
-
Useful-skew clock routing with gate sizing for low power design
-
J. G. Xi and W. W. M. Dai. Useful-skew clock routing with gate sizing for low power design. In Proc. 33rd DAC, pages 383-388, 1996.
-
(1996)
Proc. 33rd DAC
, pp. 383-388
-
-
Xi, J.G.1
Dai, W.W.M.2
-
23
-
-
0034498423
-
Clock schedule design for minimum realization cost
-
to appear
-
T. Yoda and A. Takahashi. Clock schedule design for minimum realization cost. IEICE Transactions on Fundamentals, E83-A (12): to appear, 2000.
-
(2000)
IEICE Transactions on Fundamentals
, vol.E83-A
, Issue.12
-
-
Yoda, T.1
Takahashi, A.2
|