Performance and reliability driven clock scheduling of sequential logic circuits

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 1997, Pages 37-42

  Takahashi, Atsushi ^a   Kajitani, Yoji ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; COMPUTER SIMULATION; COMPUTER SOFTWARE; RELIABILITY; TIMING CIRCUITS;

CLOCK SCHEDULING; SOFTWARE PACKAGE LGSYNTH93;

SEQUENTIAL CIRCUITS;

EID: 0030651638     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)