Clock schedule design for minimum realization cost

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E83-A, Issue 12, 2000, Pages 2552-2557

  Yoda, Tomoyuki ^a,b   Takahashi, Atsushi ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

SEMI-SYNCHRONOUS CIRCUITS;

ALGORITHMS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT;

VLSI CIRCUITS;

EID: 0034498423     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (6)

1. R.B. Dcokar and S.S. Sapatnekar, "A graph-theoretic approach to clock skew optimization," Proc. IEEE International Symposium on Circuits and Systems, vol.1, pp.407-410, 1994.
2. J.P. Fishburn, "Clock skew optimization," IEEE Trans. Comput., vol.39, no.7, pp.945-951, 1990.
3. A. Takahashi, K. Inoue, and Y. Kajitani, "Clock-tree routing realizing a clock-schedule for semi-synchronous circuits," Proc. IEEE/ACM International Conference on Computer Aided Design, pp.2GO-2G5, 1997.
4. A. Takahashi and Y. Kajitani, "Performance and reliability driven clock scheduling of sequential logic circuits," Proc. Asia and South Pacific Design Automation Conference, pp.37-42, 1997.
5. A. Takahashi, W. Takahashi, and Y. Kajitani, "Clockrouting driven layout methodology for semi-synchronous circuit design," Proc. IEEE/ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU'97), pp.G3-GG, 1997.
6. J.G. Xi and W.W. M. Dai, "Useful-skew clock routing with gate sizing for low power design," Proc. 33rd Design Automation Conference, pp.383-388, 1996.