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Volumn E84-A, Issue 11, 2001, Pages 2705-2713

A practical clock tree synthesis for semi-synchronous circuits

Author keywords

Clock scheduling; Environmental and manufacturing conditions; Semi synchronous circuit; Various timing clock tree; Zero skew clock tree

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; ELECTRIC RESISTANCE; LOGIC GATES; LSI CIRCUITS; SIMULATED ANNEALING; STATISTICAL METHODS; TIMING CIRCUITS;

EID: 0035518646     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (8)

References (18)
  • 16
    • 85027115012 scopus 로고    scopus 로고
    • Semiconductor datasheets on the Web


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.