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Volumn E84-A, Issue 11, 2001, Pages 2705-2713
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A practical clock tree synthesis for semi-synchronous circuits
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Author keywords
Clock scheduling; Environmental and manufacturing conditions; Semi synchronous circuit; Various timing clock tree; Zero skew clock tree
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Indexed keywords
CAPACITANCE;
COMPUTER SIMULATION;
ELECTRIC NETWORK SYNTHESIS;
ELECTRIC RESISTANCE;
LOGIC GATES;
LSI CIRCUITS;
SIMULATED ANNEALING;
STATISTICAL METHODS;
TIMING CIRCUITS;
CLOCK SCHEDULING;
CLOCK TREE SYNTHESIS;
SEMI-SYNCHRONOUS CIRCUITS;
VARIOUS TIMING CLOCK TREE;
ZERO SKEW CLOCK TREE;
INTEGRATED CIRCUIT LAYOUT;
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EID: 0035518646
PISSN: 09168508
EISSN: None
Source Type: Journal
DOI: None Document Type: Article |
Times cited : (8)
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References (18)
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