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Volumn E80-A, Issue 4, 1997, Pages 689-693

Cost-radius balanced spanning/steiner trees

Author keywords

Delay; Spanning tree; Steiner tree; Vlsi layout

Indexed keywords

ALGORITHMS; DESIGN; HEURISTIC METHODS; OPTIMIZATION; SIGNAL DISTORTION; VLSI CIRCUITS;

EID: 0031117083     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (6)

References (11)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.