Practical clock tree synthesis for semi-synchronous circuits

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2000, Pages 159-164

  Toyonaga, Masahiko ^a   Kurokawa, Keiichi ^a   Yasui, Takuya ^a   Takahashi, Atsushi ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; LSI CIRCUITS;

SEMI-SYNCHRONOUS CIRCUITS;

TIMING CIRCUITS;

EID: 0033701747     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)