Testing and diagnosis of interconnect faults in cluster-based FPGA architectures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 11, 2002, Pages 1337-1343

  Harris, L G ^a   Tessier, R ^a  

^a University of Massachusetts   (United States)

Author keywords

BIST; Design for testability; Interconnect; Testing

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS; FLIP FLOP CIRCUITS; LOGIC DESIGN; TABLE LOOKUP;

INTERCONNECT FAULTS; INTERCONNECT TESTING PROBLEM; LOGIC BLOCKS;

INTEGRATED CIRCUIT TESTING;

EID: 0036864857     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.804108     Document Type: Article

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