Improving diagnostic resolution of delay faults in FPGAs by exploiting reconfigurability

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2001, Pages 215-220

  Ghosh Dastidar, J ^a   Touba, N A ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COMPUTER SYSTEM RECOVERY; CRITICAL PATH ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS;

CONFIGURATION LOGIC BLOCKS; CRITICAL PATH TRACING; RECONFIGURABILITY;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0035197598     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Critical path tracing - An alternative to fault simulation
2. A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortan
3. A systematic approach for diagnosing multiple delay faults
4. Adaptive techniques for improving delay fault diagnosis
5. A novel approach to delay-fault diagnosis
6. Digital simulation with multiple logic values
7. A new path-oriented effect-cause methodology to diagnose delay failures
8. SOPRANO: An efficient automatic test pattern generator for stuck-open faults in CMOS combinational circuits