Stochastic wire-length and delay distributions of 3-dimensional circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 208-213

  Zhang, Rongtian ^a   Roy, Kaushik ^a   Koh, Cheng Kok ^a   Janes, David B ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT INTERCONNECTS; STOCHASTIC SYSTEMS; THREE DIMENSIONAL INTEGRATED CIRCUITS; WIRE; CALCULATIONS; ELECTRIC WIRE; ERROR CORRECTION; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; PROBABILITY DENSITY FUNCTION; THREE DIMENSIONAL; VLSI CIRCUITS;

3-D INTERCONNECTS; CIRCUIT APPLICATION; CIRCUIT ARCHITECTURES; DELAY DISTRIBUTIONS; HIGHER INTEGRATION; INTERCONNECT DELAY; INTERCONNECTION COMPLEXITY; WIRE LENGTH DISTRIBUTION;

DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT;

HORIZONTAL WIRE; INTERCONNECT DISTRIBUTION; THREE DIMENSIONAL CIRCUITS; VERTICAL WIRE; WIRE LENGTH DISTRIBUTION;

EID: 0034480901     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896476     Document Type: Conference Paper

References (15)

1. Semiconductor Industry Association, The International Technology Roadmap for Semiconductors, 1999 Edition.
2. T. Kunio, K. Oyama, Y. Hayashi, and M. Morimoto, "Three Dimensional ICs, Having Four Stacked Active Device Layers", IEDM'89 Conf. Proc., pp.837-840, 1989.
3. T. Nishimura, Y. Inoue, K. Sugahara, S. Kusunoki, T. Kumamoto, M. Nakaya, Y. Horiba, and Y. Akasaka, "Three Dimensional IC for High Performance Image Signal Processor", IEDM'87 Conf. Proc., pp.111- 114, 1987.
4. J. F. Gibbsons, and K. F. Lee, "One-Gate-Wide CMOS Inverter on Laser-Recrystallized Polysilicon", IEEE Electron Device Letters, Vol. EDL-2, No. 6, pp.117-118, 1980.
5. S. Kawamura, N. Sasaki, T. Iwai, M. Nakano, and M. Takagi, "Three- Dimensional CMOS IC's Fabricated by Using Beam Recrystalliza- Tion", IEEE Electron Device Letters, Vol. EDL-4, No. 10, pp.366-368, 1983.
6. R. Zingg, J. A. Friedrich, G. W. Neudeck, and B. Hofflinger, "Three- Dimensional Stacked MOS Transistors by Localized Silicon Epitaxial Overgrowth", IEEE Transactions on Electron Devices, Vol. 37, No. 6, 1452, 1990.
7. G. W. Neudeck, S. Pae, J. P. Denton, and T. Sue, "Multiple Layers of Silicon-on-Insulator for Nanostructure Devices", Journal of Vacuum Science & Technology B, Vol. 17, No. 3, pp.994-998, 1999.
8. K. Sarawat, S. J. Souri, V. Subramanian, A. R. Joshi, and A. W. Wang, "Novel 3D Structures", Proceedings of 1999 International SOI Conference, pp.54-55, 1999.
9. P. Ramm, D. Bollman, R. Braun, R. Buchner, et al, "Three Dimensional Metalization for Vertically Integrated Circuits", Microelectronic Engineering, 37/38, pp.39-47, 1997.
10. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Reading, MA: Addison-Wesley, 1990.
11. W. Donath, "Placement and Average Interconnection Lengths of Computer Logic", IEEE Trans. Circuits and Systems, Vol. CAS-26, No. 4, pp. 272-277, Apr. 1979.
12. W. Donath, "Wire Length Distribution for Placement of Computer Logic", IBM Journal of Research and Development, Vol. 25, No. 3, pp.152-155, 1981.
13. J. A. Davis, V. K. De, and J. Meindl, "A Stochastic Wire-Length Distribution for Gigascale Integration (GSI) - Part I: Derivation and Validation", IEEE Trans. Electron Devices, Vol. 45, No. 3, pp.580-589, Mar. 1998.
14. A. Gamal, "Two-Dimensional Models for Interconnections lengths in Master Slice Integrated Circuits", IEEE Trans. Circuit Syst., Vol. CAS-26, pp.272-277, 1979.
15. C. J. Alpert and A. Devgan, "Wire Segmenting for Improved Buifer Insertion", 1997 Design Automation Conference, pp.588-593, 1997.