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Volumn , Issue , 1995, Pages 135-136
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Fully depleted dual-gated thin-film SOI P-MOSFET with an isolated buried polysilicon backgate
a
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Author keywords
[No Author keywords available]
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Indexed keywords
ANNEALING;
ELECTRIC CURRENT MEASUREMENT;
ELECTRON TRANSPORT PROPERTIES;
GATES (TRANSISTOR);
MOSFET DEVICES;
OXIDATION;
SEMICONDUCTOR GROWTH;
SILICON WAFERS;
SUBSTRATES;
THIN FILMS;
TRANSCONDUCTANCE;
VOLTAGE MEASUREMENT;
BURIED POLYSILICON BACKGATE;
EFFECTIVE HOLE MOBILITY;
EFFECTIVE INTERFACE TRAP DENSITY;
FULLY DEPLETED DUAL GATED THIN FILMS;
THRESHOLD VOLTAGE;
SILICON ON INSULATOR TECHNOLOGY;
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EID: 0029534237
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (9)
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References (3)
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