3D CMOS SOI for high performance computing

Proceedings of the International Symposium on Low Power Design

Volumn , Issue , 1998, Pages 54-58

  Abou Samra, S J ^a   Aisa, P A ^a   Guyot, A ^a   Courtois, B ^a  

^a TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LITHOGRAPHY; THREE DIMENSIONAL; TRANSISTORS;

N CHANNEL TRANSISTORS; P CHANNEL DEVICES; SYMMETRICAL T GATE TRANSISTOR;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0031628020     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)