Power trends and performance characterization of 3-Dimensional integration for future technology generations

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2001-January, Issue , 2001, Pages 217-222

  Zhang, Rongtian ^a   Roy, Kaushik ^a   Koh, Cheng Kok ^a   Janes, David B ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATION; STOCHASTIC MODELS; STOCHASTIC SYSTEMS; THREE DIMENSIONAL INTEGRATED CIRCUITS;

CIRCUIT APPLICATION; CIRCUIT ARCHITECTURES; CIRCUIT PERFORMANCE; FUTURE TECHNOLOGIES; INTERCONNECT MODELING; INTERCONNECTION COMPLEXITY; PERFORMANCE CHARACTERIZATION; VERTICAL INTEGRATION;

ELECTRIC NETWORK ANALYSIS;

EID: 28344439387     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2001.915230     Document Type: Conference Paper

References (12)

1. Semiconductor Industry Association, The International Technology Roadmap for Semiconductors, 1999 Edition.
2. S. J. Souri, K. Banerjee, A. Mehrotra, and K. C. Saraswat,: "Multiple Si Layer ICs: Motivation, Performance Analysis, and Design Implications" 37th Design Automation Conference, pp. 213-220, 2000.
3. R. Zingg, J. A. Friedrich, G. W. Neudeck, and B. Hofflinger, "Three Dimensional Stacked MOS Transistors by Localized Silicon Epitaxial Overgrowth", IEEE Transactions on Electron Devices, Vol. 37, No. 6, pp. 1452-1461, 1990.
4. G. W. Neudeck, S. Pae, J. P. Denton, and T. Sue, "Multiple Layers of Silicon-on-Insulator for Nanostructure Devices", Journal of Vacuum Science & Technology B, Vol. 17, No. 3, pp. 994-998, 1999.
5. K. Sarawat, S. J. Souri, V. Subramanian, A. R. Joshi, and A. W. Wang, "Novel 3D Structures", Proceedings of 1999 International SOI Conference, pp. 54-55, 1999.
6. P. Ramm, D. Bollman, R. Braun, R. Buchner, et al, "Three Dimensional Metalization for Vertically Integrated Circuits", Microelectronic Engineering, 37/38, pp. 39-47, 1997.
7. R. Zhang, K. Roy, and D. B. Janes, "Architecture and Performance of 3-Dimensional Circuits", IEEE International SOI Conference, pp. 44-45, 1999.
8. S. J. Abou-Samra, P. A. Aisa, A. Guyot, and B. Coutois, "3D CMOS SOI for High Performance Computing", Proceedings of 1998 International Symposium on Low Power Electronics and Design, pp. 54-58, California, 1998.
9. R. Zhang, K. Roy, C.-K. Koh, and D. B. Janes, "Stochastic Wire-Length and Delay Distributions of 3-Dimensional Circuits", Proceedings of International Conference on Computer Aided Design, pp. 208-213, 2000.
10. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Reading, MA: Addison-Wesley, 1990.
11. C. J. Alpert and A. Devgan, "Wire Segmenting for Improved Buffer Insertion", 1997 Design Automation Conference, pp. 588-pp. 593, 1997.
12. J. A. Davis, V. K. De, and J. Meindl, "A Stochastic Wire-Length Distribution for Gigascale Integration (GSI) - Part 1: Derivation and Validation", IEEE Trans. Electron Devices, Vol. 45, No. 3, pp. 580-589, Mar. 1998.