Silicon single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

IEEE Transactions on Electron Devices

Volumn 49, Issue 4, 2002, Pages 627-635

  Kim, Dae Hwan ^b   Sung, Suk Kang ^b   Kim, Kyung Rok ^b   Lee, Jong Duk ^a,b   Park, Byung Gook ^a,b   Choi, Bum Ho ^c   Hwang, Sung Woo ^c   Ahn, Doyeol ^c  

^a Seoul National University ^*

^b Seoul National University   (South Korea)

^c University of Seoul   (South Korea)

Author keywords

Controllability; Conventional lithography; Process technology; Reproducibility; Sidewall depletion gates; SOI

Indexed keywords

GATES (TRANSISTOR); LITHOGRAPHY; OPTIMIZATION; SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY; VLSI CIRCUITS;

SINGLE-ELECTRON TRANSISTORS (SET);

TRANSISTORS;

EID: 0036539033     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.992872     Document Type: Article

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