A new design scheme for logic circuits with single electron transistors

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 38, Issue 7 B, 1999, Pages 4027-4032

  Uchida, Ken ^a   Matsuzawa, Kazuya ^a   Toriumi, Akira ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

CMOS; Coulomb blockade; Dynamic logic circuits; MOSFET; SET; Single electron tunneling

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC SWITCHES; ELECTRON TUNNELING; HYBRID INTEGRATED CIRCUITS; MOSFET DEVICES; TIMING CIRCUITS; TRANSISTORS; TREES (MATHEMATICS);

COULOMB BLOCKADE DIAGRAM; GATE VOLTAGE SWING; HYBRID SIMULATOR; HYBRIDIZATION; LOAD CAPACITORS; LOGIC TREES; SINGLE ELECTRON CIRCUITS;

LOGIC DESIGN;

EID: 0033309552     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.38.4027     Document Type: Article

References (4)

1. D. V. Averin and K. K. Likharev: Single Charge Tunneling, eds. H. Grabert and M. H. Devoret (Plenum, New York, 1992) Chap. 9 p. 311.
2. K. Nakazato and J. D. White: Int. Electron Devices Meet. Tech. Dig. (1992) p. 487.
3. N. Asahi, M. Akazawa and Y. Amemiya: IEEE Trans. Electron Devices 44 (1997) 1109.
4. J. R. Tucker: J. Appl. Phys. 72 (1992) 4399.