Defect-oriented Verilog fault simulation of SoC macros using a stratified fault sampling technique

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 326-332

  Santos, M B ^a   Goncalves, F M ^a   Teixeira, I C ^a   Teixeira, J P ^a  

^a INESC   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; EMBEDDED SYSTEMS; FAILURE ANALYSIS; GATES (TRANSISTOR); SAMPLING;

DEFECT ORIENTED FAULT SIMULATION; STRUCTURAL ZOOMING; SYSTEMS ON A CHIP; VERILOG FAULT SIMULATION;

INTEGRATED CIRCUIT TESTING;

EID: 0032659637     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (37)