Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 549-553

  Santos, M B ^a   Teixeira, J P ^a  

^a INSTITUTO SUPERIOR TÉCNICO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN HIERARCHY; FAULT SIMULATION; HIGH QUALITY; OPEN DEFECTS; SYSTEM MODULES; SYSTEMS-ON-A-CHIP; VERILOG;

DESIGN; EXHIBITIONS; TOOLS;

DEFECTS;

EID: 84893629710     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761181     Document Type: Conference Paper

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