Power modeling for high-level power estimation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 1, 2000, Pages 18-29

  Gupta, Subodh ^b   Najm, Farid N ^a,c  

^a IEEE   (Canada)

^b University of Illinois at Urbana Champaign   (United States)

^c UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

POWER ESTIMATION;

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER AIDED LOGIC DESIGN; CORRELATION METHODS; ELECTRIC LOSSES; ERROR ANALYSIS; MATHEMATICAL MODELS; PROBABILITY;

VLSI CIRCUITS;

EID: 0034135612     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.820758     Document Type: Article

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