Cellular automata for weighted random pattern generation

IEEE Transactions on Computers

Volumn 46, Issue 11, 1997, Pages 1219-1229

  Neebel, Danial J ^a,b   Kime, Charles R ^a,c  

^a IEEE   (United States)

^b JAMES MADISON UNIVERSITY   (United States)

^c University of Wisconsin Madison   (United States)

Author keywords

Built in self test; Cellular automata; Hybrid cellular automata; Multiple weight sets; Test per clock pattern generation; Weighted cellular automata; Weighted random patterns

Indexed keywords

AUTOMATA THEORY; COMPUTER CIRCUITS; RANDOM PROCESSES;

BUILT IN SELF TEST (BIST); CELLULAR AUTOMATA; DESIGN FOR TESTABILITY (DFT); WEIGHTED RANDOM PATTERN GENERATION;

INTEGRATED CIRCUIT TESTING;

EID: 0031380202     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.644297     Document Type: Article

References (22)

1. A.P. Ströle and H.-J. Wunderlich, "TESTCHIP: A Chip for Weighted Random Pattern Generation, Evaluation, and Test Control," IEEE J. Solid-State Circuits, vol. 26, no. 7, pp. 1,056-1,063, July 1991.
2. H.D. Schnurmann, E. Lindbloom, and R.G. Carpenter, "The Weighted Random Test-Generator," IEEE Trans. Computers, vol. 24, no. 7, pp. 695-700, July 1975.
3. H.-J. Wunderlich, "PROTEST: A Tool for Probabilistic Testability Analysis," Design Automation Conf. Proc., pp. 204-211. IEEE/ ACM, 1985.
4. F. Siavoshi, "WTPGA: A Novel Weighted Test-Pattern Generation Approach for VLSI Built-In Self Test," Proc. Int'l Test Conf., pp. 256-262. IEEE, 1988.
5. S. Bou-Ghazale and P.N. Marinos, "Testing with Correlated Test Vectors," Digest Int'l Symp. Fault-Tolerant Computing, pp. 254-262. IEEE, 1992.
6. J.A. Waicukauski, E. Lindboom, E.B. Eichelberger, and O.P. Forlenza, "A Method for Generating Weighted Random Test Patterns," IBM J. Research & Development, vol. 33, no. 2, pp. 149-161, Mar. 1989.
7. J. Hartmann and G. Kemnitz, "How to Do Weighted Random Testing for BIST?" Digest Int'l Conf. Computer-Aided Design, pp. 568-571. IEEE, 1993.
8. F. Brglez, C.S. Gloster, and G. Kedem, "Hardware-Based Weighted Random Pattern Generation for Boundary Scan," Proc. Int'l Test Conf., pp. 264-274. IEEE, 1989.
9. F. Muradali, V.K. Agarwal, and B. Nadeau-Dostie, "A New Procedure for Weighted Random Built-in Self-Test," Proc. Int'l Test Conf., pp. 660-669. IEEE, 1990.
10. H.-J. Wunderlich, "Self Test Using Unequiprobable Random Patterns," Digest Int'l Symp. Fault-Tolerant Computing, pp. 258-263. IEEE, 1987.
11. D.J. Neebel and C.R. Kime, "Inhomogeneous Cellular Automata for Weighted Random Pattern Generation," Proc. Int'l Test Conf., pp. 1,013-1,022. IEEE, 1993.
12. W. Pries, A. Thanailakis, and H.C. Card, "Group Properties of Cellular Automata and VLSI Applications," IEEE Trans. Computers, vol. 35, no. 12, pp. 1,013-1,024, Dec. 1986.
13. P.D. Hortensius, R.D. McLeod, W. Pries, D.M. Miller, and H.C. Card, "Cellular Automata-Based Pseudorandom Number Generators for Built-in Self-Test," IEEE Trans. Computer-Aided Design, vol. 8, no. 8, pp. 842-859, Aug. 1989.
14. P.D. Hortensius, "Parallel Computation of Non-Deterministic Algorithms in VLSI," PhD dissertation, Univ. of Manitoba, Manitoba, Canada, 1987.
15. D.J. Neebel, "Cellular Automata for Weighted Random Pattern Generation," PhD dissertation, Univ. of Wisconsin-Madison, Dept. of Electrical and Computer Eng., May 1994.
16. D.J. Neebel and C.R. Kime, "Multiple Weighted Cellular Automata," Proc. VLSI Test Symp., pp. 81-86. IEEE, 1994.
17. B.S. So and C.R. Kime, "A Fault Simulation Method: Parallel Pattern Critical Path Tracing," J. Electronic Testing: Theory and Applications, vol. 4, pp. 255-265, 1993.
18. P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Trans. Computers, vol. 30, no. 3, pp. 215-222, Mar. 1981.
19. J. Savir and P.H. Bardell, "On Random Pattern Test Length," IEEE Trans. Computers, vol. 33, no. 6, pp. 467-474, June 1984.
20. F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Designs and a Special Translator in Fortran," Digest Int'l Symp. Circuits and Systems, pp. 151-158. IEEE, 1985.
21. F. Brglez, D. Bryan, and K. Kozminski, "Accelerated ATPG and Fault Grading via Testability Analysis," Digest Int'l Symp. Circuits and Systems, pp. 1,929-1,934. IEEE, 1989.
22. M. Bershteyn, "Calculation of Multiple Sets of Weights for Weighted Random Testing," Proc. Int'l Test Conf., pp. 1,031-1,040. IEEE, 1993.