RT level power analysis

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 1997, Pages 517-522

  Zhu, Jianwen ^a   Agrawal, Poonam ^a   Gajski, Daniel D ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ENERGY DISSIPATION; ESTIMATION; INTEGRATED CIRCUIT TESTING; SEMICONDUCTOR DEVICE MODELS;

REGISTER TRANSFER LEVEL DATAPATH;

CMOS INTEGRATED CIRCUITS;

EID: 0030672612     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)