Design and synthesis of low power weighted random pattern generator considering peak power reduction

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1999, Pages 148-156

  Zhang, Xiaodong ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATA THEORY; BUILT-IN SELF TEST; CONSTRAINT THEORY; ELECTRIC LOSSES; ELECTRIC NETWORK SYNTHESIS; FORMAL LOGIC; INTEGRATED CIRCUIT TESTING; POWER CONTROL; SWITCHING THEORY;

LINEAR CELLULAR AUTOMATA (CA); LOW POWER AUTOMATIC TEST PATTERN GENERATORS (LPATPG);

INTEGRATED CIRCUIT LAYOUT;

EID: 0033311810     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)