Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load

Analog Integrated Circuits and Signal Processing

Volumn 14, Issue 1-2, 1997, Pages 29-39

  Adler, Victor ^a,b,c,d   Friedman, Eby G ^{a,e,f,g,h,i,j,k}  

^a University of Rochester   (United States)

^b DUKE UNIVERSITY   (United States)

^c UNIVERSITY OF ROCHESTER   (United States)

^d IBM MICROELECTRONICS   (United States)

^e LAFAYETTE COLLEGE   (United States)

^f UNIVERSITY OF CALIFORNIA   (United States)

^g PHILIPS RESEARCH LABORATORIES   (Germany)

^h RAYTHEON COMPANY   (United States)

ⁱ High Perf VLSI/Des and Anal Lab   (United States)

^j IEEE   (United States)

^k VLSI Syst Applic CAS Tech Comm   (United States)

more..

Author keywords

CMOS inverter model; Interconnect; Interconnect delay; Power dissipation; Short circuit power

Indexed keywords

DELAY CIRCUITS; ELECTRIC INVERTERS; ELECTRIC LOADS; ENERGY DISSIPATION; MATHEMATICAL MODELS; SHORT CIRCUIT CURRENTS; SIMULATION; TRANSIENTS;

SHORT CIRCUIT POWER;

CMOS INTEGRATED CIRCUITS;

EID: 0031234331     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1007/978-1-4615-6101-9_3     Document Type: Article

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