Repeater insertion in tree structured inductive interconnect

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 420-424

  Ismail, Yehea I ^a   Friedman, Eby G ^a   Neves, Jose L ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ELECTRIC DELAY LINES; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; OPTIMIZATION; TREES (MATHEMATICS); VLSI CIRCUITS;

INDUCTIVE INTERCONNECT; PATH DELAY; REPEATER INSERTION ALGORITHM;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033318406     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)