Study of test quality/tester scan memory trade-offs using the SEMATECH test methods data

IEEE International Test Conference (TC)

Volumn , Issue , 1999, Pages 839-847

  Butler, Kenneth M ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; ERROR DETECTION; INTEGRATED CIRCUIT LAYOUT; MONOLITHIC INTEGRATED CIRCUITS; STORAGE ALLOCATION (COMPUTER);

SEMATECH TEST METHODS; TEST QUALITY; TESTER SCAN MEMORY;

INTEGRATED CIRCUIT TESTING;

EID: 0033352156     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)