Shaping a VLSI wire to minimize Elmore delay

Proceedings of European Design and Test Conference

Volumn , Issue , 1997, Pages 244-251

  Fishburn, John P ^a  

^a NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DIFFERENTIAL EQUATIONS; DIFFERENTIATION (CALCULUS); ELECTRIC RESISTANCE; INTEGRATED CIRCUIT LAYOUT; LADDER NETWORKS;

ELMORE DELAY; EULER'S DIFFERENTIAL EQUATIONS;

VLSI CIRCUITS;

EID: 0030651834     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)