Optimal wire sizing and buffer insertion for low power and a generalized delay model

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1995, Pages 138-143

  Lillis, John ^a   Cheng, Chung Kuan ^a   Lin, Ting Ting Y ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; OPTIMIZATION;

BUFFER INSERTION; TIMING OPTIMIZATION; WIRE SIZING;

VLSI CIRCUITS;

EID: 0029516536     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)