System-level test synthesis for mixed-signal designs

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 48, Issue 6, 2001, Pages 588-599

  Ozev, Sule ^b   Orailoglu, Alex ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Mixed signal systems; Parameter tolerances; Probabilistic fault coverage; System level test

Indexed keywords

ANALOG SYSTEMS; BLOCK LEVEL TESTS; HIERARCHICAL TEST SYNTHESIS; MIXED SIGNAL SYSTEMS; PARAMETER TOLERANCES; PROBABILISTIC FAULT COVERAGE; SYSTEM LEVEL TEST;

CALCULATIONS; COMPUTATIONAL COMPLEXITY; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; LINEAR INTEGRATED CIRCUITS; MATHEMATICAL MODELS; PROBABILITY; SYSTEMS ANALYSIS;

DESIGN FOR TESTABILITY;

EID: 0035355354     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.943329     Document Type: Article

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