Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 1, 2001, Pages 140-158

  Srinivasan, Vinoo ^b   Govindarajan, Sriram ^c   Vemuri, Ranga ^a,d  

^a IEEE   (United States)

^b INTEL CORPORATION   (United States)

^c CADENCE DESIGN SYSTEMS   (United States)

^d University of Cincinnati   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BEHAVIORAL PARTITIONING; CONTROL DATA FLOW GRAPH; DATAFLOW GRAPH; DESIGN SPACE EXPLORATION; RECONFIGURABLE COMPUTERS;

COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS; SCHEDULING;

PROGRAM DIAGNOSTICS;

EID: 0035242911     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.920829     Document Type: Article

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