Technique for dynamic high-level exploration during behavioral-partitioning for multi-device architectures

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2000, Pages 212-219

  Govindarajan, Sriram ^a   Srinivasan, Vinoo ^a   Lakshmikanthan, Preetham ^a   Vemuri, Ranga ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; HEURISTIC PROGRAMMING; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; SIMULATED ANNEALING;

BEHAVIORAL PARTITIONING; DYNAMIC HIGH LEVEL EXPLORATION; FIDUCCIAMATTHEYSES; HIGH LEVEL SYNTHESIS; MULTIDEVICE ARCHITECTURES;

VLSI CIRCUITS;

EID: 0033884453     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)