Multi-way netlist partitioning into heterogeneous FPGAs and minimization of total device cost and interconnect

Proceedings - Design Automation Conference

Volumn , Issue , 1994, Pages 238-243

  Kuznar, Roman ^a   Brglez, Franc ^a   Zajc, Baldomir ^a  

^a UNIVERSITY OF LJUBLJANA   (Slovenia)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONFORMAL MAPPING; ELECTRIC WIRING; GRAPH THEORY; LOGIC CIRCUITS; LOGIC DESIGN; LOGIC GATES; OPTIMIZATION; SWITCHING FUNCTIONS;

BENCHMARK CIRCUITS; CONFIGURABLE LOGIC BLOCKS; ELEMENTARY CIRCUIT UNITS; FIELD PROGRAMMABLE GATE ARRAYS; FUNCTIONAL REPLICATION;

MINIMIZATION OF SWITCHING NETS;

EID: 0028602205     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/196244.196364     Document Type: Conference Paper

References (17)