Multiple FPGA partitioning with performance optimization

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 1995, Pages 146-152

  Roy Neogi, Kalapi ^a   Sechen, Carl ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CONSTRAINT THEORY; LOGIC DESIGN; MULTICHIP MODULES; PERFORMANCE; TECHNOLOGY;

FIELD PROGRAMMABLE GATE ARRAY PARTITIONING; LONGEST PATH DELAY; PARTITIONER; PERFORMANCE OPTIMIZATION; TECHNOLOGY MAPPING; TIMING CONSTRAINTS;

LOGIC CIRCUITS;

EID: 0029203682     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/201310.201333     Document Type: Conference Paper

References (23)