Multi-way partitioning for minimum delay for look-up table based FPGAs

Proceedings - Design Automation Conference

Volumn , Issue , 1995, Pages 201-205

  Sawkar, Prashant ^a   Thomas, Donald ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; GRAPH THEORY; MICROPROCESSOR CHIPS; SIMULATED ANNEALING; TABLE LOOKUP;

ACYCLIC GRAPH; CHIP CROSSINGS; COMBINATIONAL BOOLEAN NETWORK; FIELD PROGRAMMABLE GATE ARRAYS; MULTIWAY PARTITIONING; SET COVER BASED APPROACH;

COMPUTER AIDED LOGIC DESIGN;

EID: 0029216310     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/217474.217530     Document Type: Conference Paper

References (5)