Task-level partitioning and RTL design space exploration for multi-FPGA architectures

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1999, Pages 272-273

  Srinivasan, Vinoo ^a   Vemuri, Ranga ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; FAST FOURIER TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS; GENETIC ALGORITHMS; INTERCONNECTION NETWORKS; LOGIC GATES; SIMULATED ANNEALING;

ITERATIVE PARTITIONING ENGINE; REGISTER TRANSFER LEVEL DESIGN; SYSTEM FOR MULTI-FPGA PARTITIONING AND DESIGN SPACE EXPLORATION;

LOGIC DESIGN;

EID: 0033488537     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. N. Kumar, V. Srinivasan, and R. Vemuri. "Hierarchical Behavioral Partitioning for Multi Component Synthesis". In Proc. European Design Automation Conference, pages 212-219, 1996.
2. S. Kirkpatrick, C.D. Gelatt, M.P. Vecchi. "Optimization by Simulated Annealing". In Science, vol 220, no. 4598, pages 671-680, 1983.
3. Holland J. "Adaptation in Natural and Artificial Systems". Ann Arbor: University of Michigan Press, 1975.
4. "Wildforce". "WILDFORCE Reference Manual, Document #11849-0000". Annapolis Micro Systems, Inc.
5. I. Ouaiss, et.al. "An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures". In Proceedings of Parallel and Distributed Processing, pages 31-36. Springer, March 1998.