Optimized test circuits for SER characterization of a manufacturing process

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 2, 2000, Pages 142-148

  Hazucha, Peter ^a   Svensson, Christer ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; SENSORS;

SINGLE EVENT UPSET; SOFT ERROR RATE (SER);

INTEGRATED CIRCUIT TESTING;

EID: 0033900509     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.823440     Document Type: Article

References (24)

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