Sub-1 V triple-threshold CMOS/SIMOX circuit for active power reduction

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 190-191,-436

  Fujii, Koji ^a   Douseki, Takakuni ^a   Harada, Mitsuru ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMPUTER SIMULATION; ION IMPLANTATION; LEAKAGE CURRENTS; LOGIC GATES; MOSFET DEVICES;

ACTIVE POWER REDUCTION; SEPARATION BY IMPLANTATION OF OXYGEN (SIMOX);

CMOS INTEGRATED CIRCUITS;

EID: 0031675317     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)