A low power data storage circuit with an intermittent power supply scheme for Sub-1 VMT-CMOS LSIs

IEICE Transactions on Electronics

Volumn E80-C, Issue 12, 1997, Pages 1572-1577

  Akamatsu, Hironori ^a   Iwata, Toru ^a   Yamauchi, Hiroyuki ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

Data storage circuit; Intermittent connection; L volt; MT CMOS; Multiple threshold; SRAM; Virtual power line

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LSI CIRCUITS;

STATIC RANDOM ACCESS MEMORY (SRAM);

DATA STORAGE EQUIPMENT;

EID: 0031367089     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (5)

1. S.Mutoh, T.Douseki, Y.Matsuya, T.Aoki, and J.Yamada, "1-V high-speed digital circuit technology with 0.5 |jm multi-threshold CMOS," Proc. IEEE 1993 International ASIC Conf., pp. 186- 189, Sept. 1993
2. M.Horiguchi, T.Sakata, and K.Iloh, "Switched-source-impedance CMOS circuit for low standby subthreshold current gigascale LSIs," IEEE J. Solid-State Circuits, vol.28, no. 11, pp. 1131 - 1135, Nov. 1993
3. S.Shigematsu, S.Mutoh, Y.Matsuya, and J.Yamada, "A 1-V highspeed MTCMOS circuit scheme for power-down applications," Symp. on VLSI Circuits, pp. 125-126, June 1995
4. H.Akamatsu, T.Iwata, H.Yamamoto, T.Hirata, H.Yamauchi, H.Kotani, and A.Matsuzawa, "A low power data holding circuit with an intermittent power supply scheme for sub-1 V MTCMOS LSIs," Symp. on VLSI Circuits, pp. 14-15, June 1996
5. H.Yamauchi, T.Iwata, H.Akamatsu, and A.Matsuzawa, "A 0.8 V /100 MHz/sub-5 mW-operated mega-bit SRAM cell archi-lecture with charge-recycle offset-source driving (OSD) scheme," Symp. on VLSI Circuits, pp. 126-127, June 1996.