A 0.5-V MTCMOS/SIMOX logic gate

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 10, 1997, Pages 1604-1609

  Douseki, Takakuni ^a   Shigematsu, Satoshi ^a   Yamada, Junzo ^a   Harada, Mitsuru ^a   Inokawa, Hiroshi ^a   Tsuchiya, Toshiaki ^a  

^a NTT CORPORATION   (Japan)

Author keywords

CMOS digital integrated circuits; CMOSFET logic devices; Low voltage circuits; Power control; Silicon oninsulator technology

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LOGIC DEVICES; LOGIC GATES; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY;

CMOS DIGITAL INTEGRATED CIRCUITS; LOW VOLTAGE CIRCUITS; THRESHOLD VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0031256946     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.634672     Document Type: Article

References (10)

1. K. Seta, H. Hara, T. Kuroda, M. Kakumu, and T. Sakurai, "50% active-power saving without speed degradation using standby power reduction (SPR) circuit," in ISSCC Dig. Tech. Papers, 1995, pp. 84-85.
2. M. Mizuno, K. Furuta, S. Narita, H. Abiko, I. Sakai, and M. Yamashina, "Elastic-Vt CMOS circuits for multiple on-chip power control," in ISSCC Dig. Tech. Papers, 1996, pp. 300-301.
3. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, and J. Yamada, "1-V high-speed digital circuit technology with 0.5-μm multi-threshold CMOS," in Proc. IEEE 1993 Int. ASIC Conf., 1993, pp. 186-189.
4. S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, and J. Yamada, "A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application," in ISSCC Dig. Tech. Papers, 1996, pp. 168-169.
5. J. B. Burr and J. Shott, "A 200 mV self-testing encoder/decoder using Stanford ultra-low-power CMOS," in ISSCC Dig. Tech. Papers, 1994, pp. 84-85.
6. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, "Design of Ion-implanted MOSFET's with very small physical dimensions," IEEE J. Solid-State Circuits, vol. SC-9, pp. 256-268, Oct. 1974.
7. T. Douseki, S. Shigematsu, Y. Tanabe, M. Harada, H. Inokawa, and T. Tsuchiya, "A 0.5 V SIMOX-MTCMOS circuit with 200 ps logic gate," in ISSCC Dig. Tech. Papers, 1996, pp. 84-85.
8. 2 layers formed by oxygen implantation into silicon," Electron. Lett., vol. 14, no. 18, pp. 593-594, Aug. 1978.
9. F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and C. Hu, "A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation," in IEDM Tech. Dig., 1994, pp. 809-812.
10. M. Harada, T. Douseki, and T. Tsuchiya, "Suppression of threshold voltage variation in MTCMOS/SIMOX circuit operating below 0.5 V," in Proc. 1996 IEEE Symp. VLSI Technology, pp. 96-97.