-
1
-
-
0031648803
-
VESI design and implementation fuels the signal pro-cessing revolution,"
-
15, pp. 22-37, Jan. 1998
-
The Design Implementation of Signal Processing Systems Technical Committee VESI design and implementation fuels the signal pro-cessing revolution," IEEE Signal Processing Mag., 15, pp. 22-37, Jan. 1998.
-
IEEE Signal Processing Mag.
-
-
Committee, T.D.1
-
2
-
-
33749910229
-
-
P. Eapsley, J. Bier, A. Shoham, and E. A. Eee, DSP Processor Fundamentals. Berkeley, CA: Berkeley Design Technology, 1994.
-
DSP Processor Fundamentals. Berkeley, CA: Berkeley Design Technology, 1994.
-
-
Eapsley, P.1
Bier, J.2
Shoham, A.3
Eee, E.A.4
-
3
-
-
0024096640
-
Programmable DSP architectures-Part I,"
-
5, Oct. 1988
-
E. A. Eee Programmable DSP architectures-Part I," IEEE ASSP Mag., 5, Oct. 1988.
-
IEEE ASSP Mag.
-
-
Eee, E.A.1
-
4
-
-
34250864336
-
Programmable DSP architectures-Part II,"
-
6, Jan. 1988
-
_Programmable DSP architectures-Part II," IEEE ASSP Mag., 6, Jan. 1988.
-
IEEE ASSP Mag.
-
-
-
6
-
-
33749970888
-
DSP's, GPP's, and multimedia applications-An evaulation using DSPstone," in
-
V. Zivojnovic, H. Schraut, M. Willems, and H. Meyr DSP's, GPP's, and multimedia applications-An evaulation using DSPstone," in Proc. Int. Conf. Signal Processing Applications and Technology, Nov. 1995.
-
Proc. Int. Conf. Signal Processing Applications and Technology, Nov. 1995.
-
-
Zivojnovic, V.1
Schraut, H.2
Willems, M.3
Meyr, H.4
-
7
-
-
33749921693
-
Ptolemy: A framework for simulating and prototyping heterogeneous systems,"
-
J. T. Buck, S. Ha, E. A. Eee, and D. G. Messerschmitt Ptolemy: A framework for simulating and prototyping heterogeneous systems," Int. J. Comput. Simulation, Jan. 1994.
-
Int. J. Comput. Simulation, Jan. 1994.
-
-
Buck, J.T.1
Ha, S.2
Eee, E.A.3
Messerschmitt, D.G.4
-
9
-
-
84939698077
-
Synchronous dataflow,"
-
75, pp. 1235-1245, Sept. 1987
-
E. A. Eee and D. G. Messerschmitt Synchronous dataflow," Proc. IEEE, 75, pp. 1235-1245, Sept. 1987.
-
Proc. IEEE
-
-
Eee, E.A.1
Messerschmitt, D.G.2
-
11
-
-
33749918535
-
-
S. S. Bhattacharyya, P. K. Murthy, and E. A. Eee, Software Synthesis from Dataflow Graphs. Norwell, MA: Kluwer, 1996.
-
Software Synthesis from Dataflow Graphs. Norwell, MA: Kluwer, 1996.
-
-
Bhattacharyya, S.S.1
Murthy, P.K.2
Eee, E.A.3
-
12
-
-
0028996809
-
Scheduling for optimum data memory compaction in block diagram oriented software synthesis," in
-
S. Ritz, M. Willems, and H. Meyr Scheduling for optimum data memory compaction in block diagram oriented software synthesis," in Proc. Int. Conf. Acoustics, Speech, and Signal Processing, May 1995.
-
Proc. Int. Conf. Acoustics, Speech, and Signal Processing, May 1995.
-
-
Ritz, S.1
Willems, M.2
Meyr, H.3
-
13
-
-
0023138886
-
Static scheduling of synchronous dataflow programs for digital signal processing,"
-
C-36, Feb. 1987
-
E. A. Eee and D. G. Messerschmitt Static scheduling of synchronous dataflow programs for digital signal processing," IEEE Trans. Comput., C-36, Feb. 1987.
-
IEEE Trans. Comput.
-
-
Eee, E.A.1
Messerschmitt, D.G.2
-
14
-
-
0024771181
-
Gabriel: A design environment for DSR"
-
37, Nov. 1989
-
E. A. Eee, W. H. Ho, E. Goei, J. Bier, and S. S. Bhattacharyya Gabriel: A design environment for DSR" IEEE Trans. Acoust., Speech, Signal Processing, 37, Nov. 1989.
-
IEEE Trans. Acoust., Speech, Signal Processing
-
-
Eee, E.A.1
Ho, W.H.2
Goei, E.3
Bier, J.4
Bhattacharyya, S.S.5
-
15
-
-
33749958672
-
-
D. R. O'Hallaron The ASSIGN parallel program generator," School of Comput. Sei., Carnegie Mellon Univ., Pittsburgh, PA, Tech. Rep., May 1991.
-
The ASSIGN parallel program generator," School of Comput. Sei., Carnegie Mellon Univ., Pittsburgh, PA, Tech. Rep., May 1991
-
-
O'Hallaron, D.R.1
-
16
-
-
0028996572
-
Cyclostatic data flow," in
-
G. Busen, M. Engels, R. Eauwereins, and J. A. Peperstraete Cyclostatic data flow," in Proc. Int. Conf. Acoustics, Speech, and Signal Pro-cessing, May 1995, pp. 3255-3258.
-
Proc. Int. Conf. Acoustics, Speech, and Signal Pro-cessing, May 1995, Pp. 3255-3258.
-
-
Busen, G.1
Engels, M.2
Eauwereins, R.3
Peperstraete, J.A.4
-
17
-
-
0030081339
-
Cyclo-static dataflow,"
-
44, pp. 39708, Feb. 1996
-
_Cyclo-static dataflow," IEEE Trans. Signal Processing, 44, pp. 39708, Feb. 1996.
-
IEEE Trans. Signal Processing
-
-
-
19
-
-
84944275353
-
A comparison of synchronous and cyclo-static dataflow," in
-
T. M. Parks, J.E. Pino, and E. A. Eee A comparison of synchronous and cyclo-static dataflow," in Proc. IEEE Asilomar Conf. Signals, Systems, and Computers, Nov. 1995.
-
Proc. IEEE Asilomar Conf. Signals, Systems, and Computers, Nov. 1995.
-
-
Parks, T.M.1
Pino, J.E.2
Eee, E.A.3
-
22
-
-
0027152911
-
Representing and exploiting data parallelism using multi-dimensional dataflow diagrams," in
-
E. A. Eee Representing and exploiting data parallelism using multi-dimensional dataflow diagrams," in Proc. Int. Conf. Acoustics, Speech, and Signal Processing, Apr. 1993, pp. 453156.
-
Proc. Int. Conf. Acoustics, Speech, and Signal Processing, Apr. 1993, Pp. 453156.
-
-
Eee, E.A.1
-
23
-
-
0029726566
-
An extension of multidimensional synchronous dataflow to handle arbitrary sampling lattices," in
-
P. K. Murthy and E. A. Eee An extension of multidimensional synchronous dataflow to handle arbitrary sampling lattices," in Proc. Int. Conf. Acoustics, Speech, and Signal Processing, May 1996, pp. 3306-3309.
-
Proc. Int. Conf. Acoustics, Speech, and Signal Processing, May 1996, Pp. 3306-3309.
-
-
Murthy, P.K.1
Eee, E.A.2
-
24
-
-
80455123249
-
Well-behaved programs for DSP computation," in
-
G. R. Gao, R. Govindarajan, and P. Panangaden Well-behaved programs for DSP computation," in Proc. Int. Conf. Acoustics, Speech, and Signal Processing, Mar. 1992.
-
Proc. Int. Conf. Acoustics, Speech, and Signal Processing, Mar. 1992.
-
-
Gao, G.R.1
Govindarajan, R.2
Panangaden, P.3
-
25
-
-
33744743440
-
Scheduling dynamic dataflow graphs using the token flow model," in
-
J. T. Buck and E. A. Lee Scheduling dynamic dataflow graphs using the token flow model," in Proc. Int. Conf. Acoustics, Speech, and Signal Processing, Apr. 1993.
-
Proc. Int. Conf. Acoustics, Speech, and Signal Processing, Apr. 1993.
-
-
Buck, J.T.1
Lee, E.A.2
-
27
-
-
85033660515
-
Static scheduling and code generation from dynamic dataflow graphs with integer-valued control systems," in
-
_Static scheduling and code generation from dynamic dataflow graphs with integer-valued control systems," in Proc. IEEE Asilomar Conf. Signals, Systems, and Computers, Oct. 1994.
-
Proc. IEEE Asilomar Conf. Signals, Systems, and Computers, Oct. 1994.
-
-
-
28
-
-
0033694639
-
Parameterized dataflow modeling of DSP systems," in
-
B. Bhattacharya and S. S. Bhattacharyya Parameterized dataflow modeling of DSP systems," in Proc. Int. Conf. Acoustics, Speech, and Signal Processing, Istanbul, Turkey, June 2000, pp. 1948-1951.
-
Proc. Int. Conf. Acoustics, Speech, and Signal Processing, Istanbul, Turkey, June 2000, Pp. 1948-1951.
-
-
Bhattacharya, B.1
Bhattacharyya, S.S.2
-
29
-
-
0033717232
-
Quasistatic scheduling of re-configurable dataflow graphs for DSP systems," in
-
_Quasistatic scheduling of re-configurable dataflow graphs for DSP systems," in Proc. Int. Workshop Rapid System Prototyping, Paris, France, June 2000, pp. 84-99.
-
Proc. Int. Workshop Rapid System Prototyping, Paris, France, June 2000, Pp. 84-99.
-
-
-
30
-
-
0029505276
-
Optimal parenthesization of lexical orderings for DSP block diagrams," in
-
S.S. Bhattacharyya, P. K. Murthy, and E. A. Lee Optimal parenthesization of lexical orderings for DSP block diagrams," in Proc. Int. Workshop on VLSI Signal Processing, Sakai, Osaka, Japan, Oct. 1995.
-
Proc. Int. Workshop on VLSI Signal Processing, Sakai, Osaka, Japan, Oct. 1995.
-
-
Bhattacharyya, S.S.1
Murthy, P.K.2
Lee, E.A.3
-
31
-
-
85063331549
-
Buffer memory requirements in DSP applications," in
-
M. Ade, R. Lauwereins, and J. A. Peperstraete Buffer memory requirements in DSP applications," in Proc. IEEE Workshop Rapid System Prototyping, June 1994, pp. 198-123.
-
Proc. IEEE Workshop Rapid System Prototyping, June 1994, Pp. 198-123.
-
-
Ade, M.1
Lauwereins, R.2
Peperstraete, J.A.3
-
32
-
-
0030651952
-
Data memory minimization for synchronous data flow graphs emulated on DSP-FPGA targets," in
-
_Data memory minimization for synchronous data flow graphs emulated on DSP-FPGA targets," in Proc. Design Automation Conf., June 1994, pp. 64-69.
-
Proc. Design Automation Conf., June 1994, Pp. 64-69.
-
-
-
36
-
-
0032648555
-
Synthesis of embedded software from synchronous dataflow specifications,"
-
21, no. 2, pp. 151-166, June 1999
-
S. S. Bhattacharyya, P. K. Murthy, and E. A. Lee Synthesis of embedded software from synchronous dataflow specifications," J. VLSI Signal Processing Syst., 21, no. 2, pp. 151-166, June 1999.
-
J. VLSI Signal Processing Syst.
-
-
Bhattacharyya, S.S.1
Murthy, P.K.2
Lee, E.A.3
-
37
-
-
0037692896
-
A scheduling framework for minimizing memory requirements of multirate DSP systems represented as dataflow graphs," in
-
S. S. Bhattacharyya, J. T. Buck, S. Ha, and E. A. Lee A scheduling framework for minimizing memory requirements of multirate DSP systems represented as dataflow graphs," in Proc. Inte. Workshop VLSI Signal Processing, Veldhoven, The Netherlands, Oct. 1993.
-
Proc. Inte. Workshop VLSI Signal Processing, Veldhoven, the Netherlands, Oct. 1993.
-
-
Bhattacharyya, S.S.1
Buck, J.T.2
Ha, S.3
Lee, E.A.4
-
38
-
-
0029263022
-
Generating compact code from dataflow specifications of multirate signal processing algorithms,"
-
42, pp. 138-150, Mar. 1995
-
_Generating compact code from dataflow specifications of multirate signal processing algorithms," IEEE Trans. Circuits Syst. I, 42, pp. 138-150, Mar. 1995.
-
IEEE Trans. Circuits Syst. I
-
-
-
39
-
-
0030857755
-
APGAN and RPMC: Complementary heuristics for translating DSP block diagrams into efficient software implementations,"
-
S. S. Bhattacharyya, P. K. Murthy, and E. A. Lee APGAN and RPMC: Complementary heuristics for translating DSP block diagrams into efficient software implementations," J. Design Automat. Embedded Syst., pp. 33-60, Jan. 1997.
-
J. Design Automat. Embedded Syst., Pp. 33-60, Jan. 1997.
-
-
Bhattacharyya, S.S.1
Murthy, P.K.2
Lee, E.A.3
-
40
-
-
0031192495
-
Joint minimization of code and data for synchronous dataflow programs,"
-
11, no. 1, pp. 41-70, July 1997
-
P. K. Murthy, S. S. Bhattacharyya, and E. A. Lee Joint minimization of code and data for synchronous dataflow programs," J. Formal Methods in Syst. Design, 11, no. 1, pp. 41-70, July 1997.
-
J. Formal Methods in Syst. Design
-
-
Murthy, P.K.1
Bhattacharyya, S.S.2
Lee, E.A.3
-
41
-
-
45149127089
-
A hierarchical multiprocessor scheduling system for DSP applications," in
-
J. L. Pino, S. S. Bhattacharyya, and E. A. Lee A hierarchical multiprocessor scheduling system for DSP applications," in Proc. IEEE Asilomar Conf. Signals, Systems, and Computers, Nov. 1995, pp. 78-84.
-
Proc. IEEE Asilomar Conf. Signals, Systems, and Computers, Nov. 1995, Pp. 78-84.
-
-
Pino, J.L.1
Bhattacharyya, S.S.2
Lee, E.A.3
-
42
-
-
31844444986
-
-
P. K. Murthy and S. S. Bhattacharyya A buffer merging technique for reducing memory requirements of synchronous dataflow specifications," in Proc. Int. Symp. Systems Synthesis, San Jose, CA, 1999, to be published.
-
A buffer merging technique for reducing memory requirements of synchronous dataflow specifications," in Proc. Int. Symp. Systems Synthesis, San Jose, CA, 1999, to be published
-
-
Murthy, P.K.1
Bhattacharyya, S.S.2
-
43
-
-
0033681478
-
The CBP parameter-A useful annotation to aid block diagram compilers for DSP," in
-
S. S. Bhattacharyya and P. K. Murthy The CBP parameter-A useful annotation to aid block diagram compilers for DSP," in Proc. Int. Symp. Circuits and Systems, Geneva, Switzerland, May 2000, pp. IV-209-IV-212.
-
Proc. Int. Symp. Circuits and Systems, Geneva, Switzerland, May 2000, Pp. IV-209-IV-212.
-
-
Bhattacharyya, S.S.1
Murthy, P.K.2
-
44
-
-
84893677684
-
Shared memory implementations of synchronous dataflow specifications," in
-
P. K. Murthy and S.S. Bhattacharyya Shared memory implementations of synchronous dataflow specifications," in Proc. Design, Automation and Test in Europe Conf., Paris, France, Mar. 2000, pp. 404110.
-
Proc. Design, Automation and Test in Europe Conf., Paris, France, Mar. 2000, Pp. 404110.
-
-
Murthy, P.K.1
Bhattacharyya, S.S.2
-
45
-
-
84988790838
-
-
E. Zitzler, J. Teich, and S. S. Bhattacharyya Optimized software synthesis for DSP using randomization techniques," Comput. Eng. Commun. Networks Lab., Swiss Federal Institute of Technology, Zurich, Switzerland, Tech. Rep., July 1999.
-
Optimized software synthesis for DSP using randomization techniques," Comput. Eng. Commun. Networks Lab., Swiss Federal Institute of Technology, Zurich, Switzerland, Tech. Rep., July 1999
-
-
Zitzler, E.1
Teich, J.2
Bhattacharyya, S.S.3
-
46
-
-
0031630618
-
Optimized software synthesis for digital signal processing algorithms-An evolutionary approach," in
-
J. Teich, E. Zitzler, and S. S. Bhattacharyya Optimized software synthesis for digital signal processing algorithms-An evolutionary approach," in Proc. IEEE Workshop Signal Processing Systems, Boston, MA, Oct. 1998, pp. 589-598.
-
Proc. IEEE Workshop Signal Processing Systems, Boston, MA, Oct. 1998, Pp. 589-598.
-
-
Teich, J.1
Zitzler, E.2
Bhattacharyya, S.S.3
-
47
-
-
84988790841
-
-
E. Zitzler, J. Teich, and S. S. Bhattacharyya Evolutionary algorithms for the synthesis of embedded software," IEEE Trans. VLSI Syst., 1999, to be published.
-
Evolutionary algorithms for the synthesis of embedded software," IEEE Trans. VLSI Syst., 1999, to be published
-
-
Zitzler, E.1
Teich, J.2
Bhattacharyya, S.S.3
-
48
-
-
0031122888
-
Evolutionary computation: Comments on the history and current state,"
-
1, pp. 3-17, 1997
-
T. Back, U. Hammel, and H.-P. Schwefel Evolutionary computation: Comments on the history and current state," IEEE Trans. Evolutionary Comput., 1, pp. 3-17, 1997.
-
IEEE Trans. Evolutionary Comput.
-
-
Back, T.1
Hammel, U.2
Schwefel, H.-P.3
-
49
-
-
33749925351
-
-
V. Zivojnovic, S. Ritz, and H. Meyr Multirate retiming: A powerful tool for hardware/software codesign," Aachen Univ. Technol., Tech. Rep., 1993.
-
Multirate retiming: A powerful tool for hardware/software codesign," Aachen Univ. Technol., Tech. Rep., 1993
-
-
Zivojnovic, V.1
Ritz, S.2
Meyr, H.3
-
50
-
-
84988745858
-
Retiming of DSP programs for optimum vectorization," in
-
_Retiming of DSP programs for optimum vectorization," in Proc. Int. Conf. Acoustics, Speech, and Signal Processing, Ape, 1994.
-
Proc. Int. Conf. Acoustics, Speech, and Signal Processing, Ape, 1994.
-
-
-
52
-
-
0033892761
-
-
E. Zitzler, J. Teich, and S. S. Bhattacharyya Multidimensional exploration of software implementations for DSP algorithms," J. VLSI Signal Processing Syst., 1999, to be published.
-
Multidimensional exploration of software implementations for DSP algorithms," J. VLSI Signal Processing Syst., 1999, to be published
-
-
Zitzler, E.1
Teich, J.2
Bhattacharyya, S.S.3
-
53
-
-
33749944182
-
-
Mentor Graphics Corporation, Wilsonville, OR DSP Architect DEL User's and Reference Manual,", V 8.2_6, 1993.
-
DSP Architect del User's and Reference Manual,", V 8.2_6, 1993
-
-
Corporation, M.G.1
Wilsonville, O.R.2
-
55
-
-
33749882294
-
-
P. Paulin, M. Cornero, and C. Liem et al., "Trends in Embedded Systems Technology," in Hardware/Software Codesign, M. G. Sami and G. De Micheli, Eds. Norwell, MA: Kluwer, 1996.
-
"Trends in Embedded Systems Technology," in Hardware/Software Codesign, M. G. Sami and G. de Micheli, Eds. Norwell, MA: Kluwer, 1996
-
-
Paulin, P.1
Cornero, M.2
Liem, C.3
-
56
-
-
33749897463
-
-
K. M. Bischoff Ox User's Manual," Iowa State Univ., Ames, IA, Tech. Rep. 92-31, 1992.
-
Ox User's Manual," Iowa State Univ., Ames, IA, Tech. Rep. 92-31, 1992
-
-
Bischoff, K.M.1
-
57
-
-
33749883387
-
-
A. V. Aho, R. Sethi, and J. D. Ullman, Compilers-Principles, Techniques, and Tools. Reading, MA: Addison-Wesley, 1986.
-
Compilers-Principles, Techniques, and Tools. Reading, MA: Addison-Wesley, 1986.
-
-
Aho, A.V.1
Sethi, R.2
Ullman, J.D.3
-
59
-
-
0024750286
-
Code generation using tree matching and dynamic programming,"
-
11, no. 4, pp. 491-516, 1989
-
A. V. Aho, M. Ganapathi, and S. W. K Tjiang Code generation using tree matching and dynamic programming," ACM Trans. Programming Languages and Systems, 11, no. 4, pp. 491-516, 1989.
-
ACM Trans. Programming Languages and Systems
-
-
Aho, A.V.1
Ganapathi, M.2
Tjiang, S.W.K.3
-
60
-
-
0028056671
-
Instruction-set matching and selection for DSP and ASIP code generation," in
-
C. Liem, T. May, and P. Paulin Instruction-set matching and selection for DSP and ASIP code generation," in Proc. Eur. Design and Test Conf. (ED & TC), 1994, pp. 31-37.
-
Proc. Eur. Design and Test Conf. (ED & TC), 1994, Pp. 31-37.
-
-
Liem, C.1
May, T.2
Paulin, P.3
-
62
-
-
0026916192
-
Engineering a simple, efficient code generator generator,"
-
1, no. 3, pp. 213-226, 1992
-
C. W. Eraser, D. R. Hanson, and T. A. Proebsting Engineering a simple, efficient code generator generator," ACM Lett. Programming Lang, and Syst., 1, no. 3, pp. 213-226, 1992.
-
ACM Lett. Programming Lang, and Syst.
-
-
Eraser, C.W.1
Hanson, D.R.2
Proebsting, T.A.3
-
64
-
-
0029236381
-
Code optimization techniques for embedded DSP microprocessors," in
-
S. Liao, S. Devadas, K. Keutzer, S. Tjiang, and A. Wang Code optimization techniques for embedded DSP microprocessors," in Proc. 32nd Design Automation Conf. (DAC), 1995, pp. 599-604.
-
Proc. 32nd Design Automation Conf. (DAC), 1995, Pp. 599-604.
-
-
Liao, S.1
Devadas, S.2
Keutzer, K.3
Tjiang, S.4
Wang, A.5
-
65
-
-
0029488328
-
Instruction selection using binate covering for code size optimization," in
-
S. Liao, S. Devadas, K. Keutzer, and S. Tjiang Instruction selection using binate covering for code size optimization," in Proc. Int. Conf. Computer-Aided Design (ICCAD), 1995, pp. 393-399.
-
Proc. Int. Conf. Computer-Aided Design (ICCAD), 1995, Pp. 393-399.
-
-
Liao, S.1
Devadas, S.2
Keutzer, K.3
Tjiang, S.4
-
67
-
-
0029538798
-
Optimal register assignment for loops for embedded code generation," in
-
D. J. Kolson, A. Nicolau, N. Dutt, and K. Kennedy Optimal register assignment for loops for embedded code generation," in Proc. 8th Int. Symp. System Synthesis (ISSS), 1995.
-
Proc. 8th Int. Symp. System Synthesis (ISSS), 1995.
-
-
Kolson, D.J.1
Nicolau, A.2
Dutt, N.3
Kennedy, K.4
-
69
-
-
0026817662
-
Optimizing stack frame accesses for processors with restricted addressing modes
-
22, no. 2, pp. 101-110, 1992
-
D. H. Bartley Optimizing stack frame accesses for processors with restricted addressing modes, "Software-Practice and Experience, 22, no. 2, pp. 101-110, 1992.
-
"Software-Practice and Experience
-
-
Bartley, D.H.1
-
70
-
-
0030149574
-
Storage assignment to decrease code size," in
-
S. Liao, S. Devadas, K. Keutzer, S. Tjiang, and A. Wang Storage assignment to decrease code size," in Proc. ACM SIGPLAN Conf. Programming Language Design and Implementation (PLDI), 1995.
-
Proc. ACM SIGPLAN Conf. Programming Language Design and Implementation (PLDI), 1995.
-
-
Liao, S.1
Devadas, S.2
Keutzer, K.3
Tjiang, S.4
Wang, A.5
-
76
-
-
0019595341
-
Some experiments in local microcode compaction for horizontal machines,"
-
C-30, pp. 46CM77, 1981
-
S. Davidson, D. Landskov, B. D. Shriver, and P. W. Mallett Some experiments in local microcode compaction for horizontal machines," IEEE Trans. Comput., C-30, pp. 46CM77, 1981.
-
IEEE Trans. Comput.
-
-
Davidson, S.1
Landskov, D.2
Shriver, B.D.3
Mallett, P.W.4
-
77
-
-
0029214434
-
Conflict modeling and instruction scheduling in code generation for in-house DSP cores," in
-
A. Timmer, M. Strik, J. van Meerbergen, and J. Jess Conflict modeling and instruction scheduling in code generation for in-house DSP cores," in Proc. 32nd Design Automation Conf. (DAC), 1995, pp. 593-598.
-
Proc. 32nd Design Automation Conf. (DAC), 1995, Pp. 593-598.
-
-
Timmer, A.1
Strik, M.2
Van Meerbergen, J.3
Jess, J.4
-
82
-
-
0027929512
-
An integrated approach to retargetable code generation," in
-
T. Wilson, G. Grewal, B. Halley, and D. Banerji An integrated approach to retargetable code generation," in Proc. 7th Int. Symp. Highlevel Synthesis (HLSS). 1994, pp. 70-75.
-
Proc. 7th Int. Symp. Highlevel Synthesis (HLSS). 1994, Pp. 70-75.
-
-
Wilson, T.1
Grewal, G.2
Halley, B.3
Banerji, D.4
-
84
-
-
33749952014
-
A unified code generation approach using mutation scheduling," in
-
S. Novack, A. Nicolau, and N. Dutt A unified code generation approach using mutation scheduling," in Code Generation for Embedded Processing. Norwell, MA: Kluwer, 1995, Ch. 12.
-
Code Generation for Embedded Processing. Norwell, MA: Kluwer, 1995, Ch. 12.
-
-
Novack, S.1
Nicolau, A.2
Dutt, N.3
-
90
-
-
33749899659
-
A graph based processor model for retargetable code generation," in
-
J. Van Praet, D. Lanneer, G. Goossens, W. Geurts, and H. De Man A graph based processor model for retargetable code generation," in Proc. Ear. Design and Test Conf. (ED & TC), 1996.
-
Proc. Ear. Design and Test Conf. (ED & TC), 1996.
-
-
Van Praet, J.1
Lanneer, D.2
Goossens, G.3
Geurts, W.4
De Man, H.5
-
92
-
-
0031623719
-
Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator," in
-
S. Hanono and S. Devadas Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator," in Proc. 35th Design Automation Conf. (DAC), 1998.
-
Proc. 35th Design Automation Conf. (DAC), 1998.
-
-
Hanono, S.1
Devadas, S.2
-
94
-
-
84988768416
-
-
ACE Associated Compiler Experts, Amsterdam, The Netherlands. (1998). Online Available: http://www.ace.nl
-
ACE Associated Compiler Experts, Amsterdam, The Netherlands. (1998). Online Available: http://www.ace.nl
-
-
-
-
95
-
-
84988768420
-
-
Target Compiler Technologies, Leuven, Belgium. (1998). Online Available: http://www.retarget.com
-
Target Compiler Technologies, Leuven, Belgium. (1998). Online Available: http://www.retarget.com
-
-
-
-
96
-
-
84988751405
-
-
Archelon Inc., Ontario, Belgium, Canada. (2000). Online Available: http://www.archelon.com
-
Archelon Inc., Ontario, Belgium, Canada. (2000). Online Available: http://www.archelon.com
-
-
-
|