APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations

Design Automation for Embedded Systems

Volumn 2, Issue 1, 1997, Pages 33-60

  Bhattacharyya, Shuvra S ^a   Murthy, Praveen K ^b   Lee, Edward A ^b  

^a HITACHI AMERICA LTD   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Clustering; Dataflow programming; Dynamic programming; Memory management; Minimum cuts; Multirate signal processing algorithms; On chip memory; SDF compiler; Synchronous dataflow

Indexed keywords

ALGORITHMS; COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; DIGITAL SIGNAL PROCESSING; DYNAMIC PROGRAMMING; PROGRAM COMPILERS; PROGRAM PROCESSORS; SOFTWARE ENGINEERING;

DATAFLOW; PAIRWISE GROUPING OF ADJACENT NODES; SEMANTICS; SOFTWARE IMPLEMENTATIONS; SYNCHRONOUS DATAFLOW;

HEURISTIC PROGRAMMING;

EID: 0030857755     PISSN: 09295585     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008806425898     Document Type: Article

References (18)

1. M. Ade, R. Lauwereins and J. A. Peperstraete. Buffer memory requirements in DSP applications. IEEE Wkshp. on Rapid System Prototyping, June 1994.
2. S. S. Bhattacharyya, P. K. Murthy and E. A. Lee. Two complementary heuristics for translating graphical DSP programs into minimum memory software implementations. Memorandum UCB/ERL M95/3, Electronics Research Laboratory, University of California at Berkeley, Jan., 1995.
3. S. S. Bhattacharyya, P. K. Murthy and E. A. Lee. Software Synthesis from Dataflow Graphs. Kluwer Academic Publishers, Norwell MA, 1996.
4. S. S. Bhattacharyya and E. A. Lee. Scheduling synchronous dataflow graphs for efficient looping. Jo. of VLSI Signal Processing, Dec. 1993.
5. J. Buck, S. Ha, E. A. Lee and D. G. Messerschmitt. Ptolemy: a framework for simulating and prototyping heterogeneous systems. International Journal of Computer Simulation, Jan. 1995.
6. T. H. Cormen, C. E. Leiserson and R. L. Rivest. Introduction to Algorithms. McGraw-Hill, 1990.
7. J. Fabri. Automatic Storage Optimization. UMI Research Press, 1982.
8. M. R. Garey and D. S. Johnson. Computers and Intractability-A Guide to the Theory of NP-Completeness. Freeman, 1979.
9. R. Govindarajan, G. R. Gao and P. Desai. Minimizing memory requirements in rate-optimal schedules. Proc. of the Intl. Conf. on Application Specific Array Processors, San Francisco, Aug. 1994.
10. B. W. Kernighan and S. Lin. An efficient heuristic procedure for partitioning graphs. Bell System Technical Journal, Feb. 1970.
11. R. Lauwereins, P. Wauters, M. Ade and J. A. Peperstraete. Geometric parallelism and cyclo-static dataflow in GRAPE-II. IEEE Wkshp. on Rapid System Prototyping, June 1994.
12. E. A. Lee, W. H. Ho, E. Goei, J. Bier and S. S. Bhattacharyya. Gabriel: A design environment for DSP. IEEE Trans. on Acoustics, Speech, and Signal Processing, Nov. 1989.
13. E. A. Lee, D. G. Messerschmitt. Static scheduling of synchronous dataflow programs for digital signal processing. IEEE Trans. on Computers, Feb. 1987.
14. P. K. Murthy, S. S. Bhattacharyya and E. A. Lee. "Joint Minimization of Code and Data for Synchronous Dataflow Programs," Journal of Formal Methods in System Design, to appear in 1996.
15. D. R. O'Hallaron. The Assign Parallel Program Generator, Memorandum CMU-CS-91-141, School of Computer Science, Carnegie Mellon University, May 1991.
16. J. Pino, S. Ha, E. A. Lee and J. T. Buck. Software synthesis for DSP using Ptolemy. Invited paper in Jo. of VLSI Signal Processing, Jan. 1995.
17. S. Ritz, S. Pankert, and H. Meyr. High level software synthesis for signal processing systems. Proc. of the Intl. Conf. on Application Specific Array Processors, Aug. 1992.
18. S. Ritz, M. Willems and II. Meyr. Scheduling for optimum data memory compaction in block diagram oriented software synthesis. Proceedings of the ICASSP 95, Detroit, Michigan, May 1995.