Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets

Proceedings - Design Automation Conference

Volumn , Issue , 1997, Pages 64-69

  Ade, Marleen ^a   Lauwereins, Rudy ^a   Peperstraete, J A ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUFFER STORAGE; COMPUTER SYSTEM RECOVERY; DIGITAL SIGNAL PROCESSING; LOGIC CIRCUITS; RAPID PROTOTYPING;

FIELD PROGRAMMABLE GATE ARRAYS; SYNCHRONOUS DATA FLOW;

ALGORITHMS;

EID: 0030651952     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/266021.266036     Document Type: Conference Paper

References (12)