Instruction selection using binate covering for code size optimization

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1995, Pages 393-399

  Liao, Stan ^a   Devadas, Srinivas ^a   Keutzer, Kurt ^a   Tjiang, Steve ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GRAPH THEORY; HEURISTIC METHODS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION; PROBLEM SOLVING;

ACCUMULATOR BASED ARCHITECTURES; BINATE COVERING; CODE GENERATION; CODE SIZE OPTIMIZATION; DIRECTED ACYCLIC GRAPH (DAG) COVERING; EMBEDDED SYSTEMS; INSTRUCTION SELECTION;

DIGITAL SIGNAL PROCESSING;

EID: 0029488328     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)