-
1
-
-
0019055294
-
High-speed multiprocessors and compilation techniques.
-
Sept
-
D. A. Padua, D. J. Kuck, and D. H. Lawrie, “High-speed multiprocessors and compilation techniques.,” IEEE Trans. Cornput., vol. C-29, no. 9, pp. 763–776, Sept. 1980
-
(1980)
IEEE Trans. Comput.
, vol.C-29
, Issue.9
, pp. 763-776
-
-
Padua, D.A.1
Kuck, D.J.2
Lawrie, D.H.3
-
2
-
-
0019079721
-
Data flow supercomputers
-
Nov
-
J. B. Dennis, “Data flow supercomputers,” Computer, vol. 13, no. 11, pp. 48–56, Nov. 1980
-
(1980)
Computer
, vol.13
, Issue.11
, pp. 48-56
-
-
Dennis, J.B.1
-
3
-
-
84942487232
-
A computer architecture for highly parallel signal processing
-
J. B. Dennis and D. P. Misunas, “A computer architecture for highly parallel signal processing,” in Proc. 1974 Nat. Comput. Conf., pp. 402-409, 1974
-
(1974)
Proc. 1974 Nat. Comput. Conf.
, pp. 402-409
-
-
Dennis, J.B.1
Misunas, D.P.2
-
4
-
-
0020087076
-
A practical data flow computer
-
Feb
-
I. Watson and J. Gurd, “A practical data flow computer,” Computer, vol. 15, no. 2, pp. 51–57, Feb. 1982
-
(1982)
Computer
, vol.15
, Issue.2
, pp. 51-57
-
-
Watson, I.1
Gurd, J.2
-
5
-
-
0020087077
-
Data flow program graphs
-
Feb
-
A. L. Davis and R. M. Keller, “Data flow program graphs,” Computer, vol. 15, no. 2, pp. 26–41, Feb. 1982
-
(1982)
Computer
, vol.15
, Issue.2
, pp. 26-41
-
-
Davis, A.L.1
Keller, R.M.2
-
6
-
-
0020087049
-
Data flow languages
-
Feb
-
W. B. Ackerman, “Data flow languages,” Computer, vol. 15, no. 2, pp. 15–25, Feb. 1982
-
(1982)
Computer
, vol.15
, Issue.2
, pp. 15-25
-
-
Ackerman, W.B.1
-
7
-
-
84919080040
-
Data driven and demand driven computer architecture
-
UK, Tech. Rep
-
P. C. Treleaven, D. R. Brownbridge, and R. P. Hopkins, “Data driven and demand driven computer architecture,” University of Newcastle upon Tyne, Newcastle upon Tyne, UK, Tech. Rep., 1981
-
(1981)
University of Newcastle upon Tyne, Newcastle upon Tyne
-
-
Treleaven, P.C.1
Brownbridge, D.R.2
Hopkins, R.P.3
-
8
-
-
11844277920
-
Cyclo-static solutions: Optimal multiprocessor realizations of recursive algorithms
-
S-Y. Kung, R. E. Owen, and J. G. Nash, Eds. New York, NY: IEEE PRESS
-
D. A. Schwartz and T. P. Barnwell, III, “Cyclo-static solutions: Optimal multiprocessor realizations of recursive algorithms,” in VLSI Signal Processing, II, S-Y. Kung, R. E. Owen, and J. G. Nash, Eds. New York, NY: IEEE PRESS, 1986
-
(1986)
VLSI Signal Processing, II
-
-
Schwartz, D.A.1
Barnwell, T.P.2
-
9
-
-
0342499038
-
Synchronous multiprocessor realizations of shift-invariant flow graphs
-
Ph.D. dissertation, Georgia Inst. Technol. Tech. Rep. DSPL-85-2, July
-
D. A. Schwartz, “Synchronous multiprocessor realizations of shift-invariant flow graphs,” Ph.D. dissertation, Georgia Inst. Technol. Tech. Rep. DSPL-85-2, July 1985
-
(1985)
Tech. Rep. DSPL-85-2
-
-
Schwartz, D.A.1
-
10
-
-
84939745607
-
Optimum implementation of single time index signal flow graphs on synchronous multiprocessor machines
-
May
-
T. P. Barnwell, C. J. M. Hodges, and M. Randolf, “Optimum implementation of single time index signal flow graphs on synchronous multiprocessor machines,” in Proc. Int. Conf. on Acoustics, Speech, and Signal Processing (May 3–5, 1982)
-
(1982)
Proc. Int. Conf. on Acoustics, Speech, and Signal Processing(
, pp. 3-5
-
-
Barnwell, T.P.1
Hodges, C.J.M.2
Randolf, M.3
-
12
-
-
0019543647
-
The maximum sampling rate of digital filters under hardware speed constraints
-
Mar
-
M. Renfors and Y. Neuvo, “The maximum sampling rate of digital filters under hardware speed constraints,” IEEE Trans. Circuits and Syst., vol. CAS-28, no. 3, pp. 196–202, Mar. 1981
-
(1981)
IEEE Trans. Circuits and Syst.
, vol.CAS-28
, Issue.3
, pp. 196-202
-
-
Renfors, M.1
Neuvo, Y.2
-
13
-
-
0017907315
-
The architecture and system method of DDM1: A recursively structured data driven machine
-
Apr
-
A. L. Davis, “The architecture and system method of DDM1: A recursively structured data driven machine,” in Proc. 5th Annu. Symp. on Computer Architecture, pp. 210–215, Apr. 1978
-
(1978)
Proc. 5th Annu. Symp. on Computer Architecture
, pp. 210-215
-
-
Davis, A.L.1
-
14
-
-
0017458590
-
A data flow multiprocessor
-
Feb
-
J, Rumbaugh, “A data flow multiprocessor,” IEEE Trans. Cornput., vol. C-26, no. 2, p. 138, Feb. 1977
-
(1977)
IEEE Trans. Cornput.
, vol.C-26
, Issue.2
, pp. 138
-
-
Rumbaugh, J.1
-
15
-
-
0021458512
-
Parallel processing with large grain data flow techniques
-
July
-
R. G. Babb, “Parallel processing with large grain data flow techniques,” Computer, vol. 17, no. 7, pp. 55–61, July 1984
-
(1984)
Computer
, vol.17
, Issue.7
, pp. 55-61
-
-
Babb, R.G.1
-
16
-
-
0016990743
-
Fractional tap-spacing and consequences for clock recovery in data modems
-
Aug
-
G. Ungerboeck, “Fractional tap-spacing and consequences for clock recovery in data modems,” IEEE Trans. Commun., vol. COM-24, pp. 856–864, Aug. 1976
-
(1976)
IEEE Trans. Commun.
, vol.COM-24
, pp. 856-864
-
-
Ungerboeck, G.1
-
17
-
-
0019527989
-
Fractionally-spaced equalization: An improved digital transversal equalizer
-
Feb
-
R. D. Gitlin and S. B. Weinstein, “Fractionally-spaced equalization: An improved digital transversal equalizer,” Bell Syst. Tech. J., vol. 60, no. 2, Feb. 1981
-
(1981)
Bell Syst. Tech. J.
, vol.60
, Issue.2
-
-
Gitlin, R.D.1
Weinstein, S.B.2
-
18
-
-
0016929561
-
Jointly adaptive equalization and carrier recovery in two-dimensional digital communication systems
-
Mar
-
D. D. Falconer, “Jointly adaptive equalization and carrier recovery in two-dimensional digital communication systems,” Bell Syst. Tech. J., vol. 55, no. 3, Mar. 1976
-
(1976)
Bell Syst. Tech. J.
, vol.55
, Issue.3
-
-
Falconer, D.D.1
-
20
-
-
84926954397
-
A block diagram compiler
-
May
-
Kelly, Lochbaum, and Vyssotsky, “A block diagram compiler,” Bell Syst. Tech. J., vol. 40, no. 3, May 1961
-
(1961)
Bell Syst. Tech. J.
, vol.40
, Issue.3
-
-
Kelly, L.1
Vyssotsky, V.2
-
22
-
-
84937999144
-
The new block diagram compiler for simulation of sampled-data systems
-
B. Karafin, “The new block diagram compiler for simulation of sampled-data systems,” in AFIPS Conf. Proc., vol. 27, pp. 55–61, 1965
-
(1965)
AFIPS Conf. Proc.
, vol.27
, pp. 55-61
-
-
Karafin, B.1
-
23
-
-
84937742042
-
On-line simulation of block-diagram systems
-
Apr
-
M. Dertouzous, M. Kaliske, and K. Polzen, “On-line simulation of block-diagram systems,” IEEE Trans. Comput., vol. C-18, no. 4, pp. 333–342, Apr. 1969
-
(1969)
IEEE Trans. Comput.
, vol.C-18
, Issue.4
, pp. 333-342
-
-
Dertouzous, M.1
Kaliske, M.2
Polzen, K.3
-
24
-
-
49349137842
-
High-speed block-diagram languages for microprocessors and minicomputers in instrumentation, control, and simulation
-
G. Korn, “High-speed block-diagram languages for microprocessors and minicomputers in instrumentation, control, and simulation,” Comput. Elec. Eng., vol. 4, pp. 143-159,1977
-
(1977)
Comput. Elec. Eng.
, vol.4
, pp. 143-159
-
-
Korn, G.1
-
25
-
-
84939750747
-
MITSYN-An interactive dialogue language for time signal processing
-
Feb
-
W. Henke, “MITSYN-An interactive dialogue language for time signal processing,” MIT Res. Lab. Electron. Memo. RLETM-1, Feb. 1975
-
(1975)
MIT Res. Lab. Electron. Memo.
-
-
Henke, W.1
-
26
-
-
84939720666
-
Circus
-
Princeton, NJ, CRD Working Paper, Dec
-
T. Crystal and L. Kulsrud, “Circus,” Inst, for Defense Analysis, Princeton, NJ, CRD Working Paper, Dec. 1974
-
(1974)
Inst, for Defense Analysis
-
-
Crystal, T.1
Kulsrud, L.2
-
28
-
-
0021121558
-
A tool for structured functional simulation
-
Jan
-
D. G. Messerschmitt, “A tool for structured functional simulation,” IEEE J. Selected Areas Commun., vol. SAC-2, no. 1, pp. 137–147, Jan. 1984
-
(1984)
IEEE J. Selected Areas Commun.
, vol.SAC-2
, Issue.1
, pp. 137-147
-
-
Messerschmitt, D.G.1
-
29
-
-
84939765309
-
Structured interconnection of signal processing programs
-
Dec
-
D. G. Messerschmitt, “Structured interconnection of signal processing programs,” in Proc. Globecom84, Dec. 1984
-
(1984)
Proc. Globecom84
-
-
Messerschmitt, D.G.1
-
30
-
-
0021457540
-
Parallel programming and the Poker programming environment
-
July
-
L. Snyder, “Parallel programming and the Poker programming environment,” Computer, vol. 17, no. 7, pp. 27–36, July 1984
-
(1984)
Computer
, vol.17
, Issue.7
, pp. 27-36
-
-
Snyder, L.1
-
31
-
-
0016495267
-
Analysis of linear digital networks
-
Apr
-
R. E. Crochiere and A. V. Oppenheim, “Analysis of linear digital networks,” Proc. IEEE, vol. 63, no. 4, pp. 581–595, Apr. 1975
-
(1975)
Proc. IEEE
, vol.63
, Issue.4
, pp. 581-595
-
-
Crochiere, R.E.1
Oppenheim, A.V.2
-
32
-
-
0018024370
-
An approach to the implementation of digital filters using microprocessors
-
Oct
-
J. P. Brafman, J. Szczupak, and S. K. Mitra, “An approach to the implementation of digital filters using microprocessors,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-26, no. 5, pp. 442–446, Oct. 1978
-
(1978)
IEEE Trans. Acoust., Speech, Signal Processing
, vol.ASSP-26
, Issue.5
, pp. 442-446
-
-
Brafman, J.P.1
Szczupak, J.2
Mitra, S.K.3
-
33
-
-
0020950737
-
Systematic design and programming of signal processors, using project management techniques
-
Dec
-
J. Zeman and G. S. Moschytz, “Systematic design and programming of signal processors, using project management techniques,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-31 no. 6, pp. 1536–1549, Dec. 1983
-
(1983)
IEEE Trans. Acoust., Speech, Signal Processing
, vol.ASSP-31
, Issue.6
, pp. 1536-1549
-
-
Zeman, J.1
Moschytz, G.S.2
-
34
-
-
84939341542
-
Heirarchical iterative flowgraph integration for VLSI array processers
-
P. R. Capello et al., Eds. New York, NY: IEEE PRESS
-
S. Y. Kung, J. Annevelink, and D. Dewilde, “Heirarchical iterative flowgraph integration for VLSI array processers,” in VLSI Signal Processing, P. R. Capello et al., Eds. New York, NY: IEEE PRESS, 1984, pp. 294–305
-
(1984)
VLSI Signal Processing
, pp. 294-305
-
-
Kung, S.Y.1
Annevelink, J.2
Dewilde, D.3
-
36
-
-
0000596527
-
Scheduling parallel computations
-
R. Reiter, “Scheduling parallel computations,” J. Assoc. Comput Mach., vol. 14, pp. 590-599, 1968
-
(1968)
J. Assoc. Comput Mach.
, vol.14
, pp. 590-599
-
-
Reiter, R.1
-
37
-
-
0006942731
-
A coupled hardware and software architecture for programmable digital signal processors
-
UC Berkeley
-
E. A. Lee, “A coupled hardware and software architecture for programmable digital signal processors,” Ph.D. dissertation, Memo. UCB/ERL M86/54, EECD Dept., UC Berkeley, 1986
-
(1986)
Ph.D. dissertation, Memo. UCB/ERL M86/54, EECD Dept.
-
-
Lee, E.A.1
-
38
-
-
0001512318
-
The organization of computations for uniform recurrence equations
-
R. M. Karp, R. E. Miller, and S. Winograd, “The organization of computations for uniform recurrence equations,” J. Assoc. Comput. Mach., vol. 14, pp. 563-590, 1967
-
(1967)
J. Assoc. Comput. Mach.
, vol.14
, pp. 563-590
-
-
Karp, R.M.1
Miller, R.E.2
Winograd, S.3
-
39
-
-
0003496098
-
Regular iterative algorithms and their implementations on processor arrays
-
Stanford Univ., Stanford, CA, Oct
-
S. K. Rao, “Regular iterative algorithms and their implementations on processor arrays,” Ph.D. dissertation, Informat. Sys. Lab., Stanford Univ., Stanford, CA, Oct. 1985
-
(1985)
Ph.D. dissertation, Informat. Sys. Lab.
-
-
Rao, S.K.1
-
40
-
-
0003762771
-
Properties of a model for parallel computations: Determinacy, termination, queueing
-
Nov
-
R. M. Karp and R. E. Miller, “Properties of a model for parallel computations: Determinacy, termination, queueing,” SIAM J., vol. 14, pp. 1390–1411, Nov. 1966
-
(1966)
SIAM J.
, vol.14
, pp. 1390-1411
-
-
Karp, R.M.1
Miller, R.E.2
-
41
-
-
84909459626
-
A study of a model for parallel computations
-
Michigan, Ann Arbor
-
R. Reiter, “A study of a model for parallel computations,” Ph.D. dissertation, Univ. Michigan, Ann Arbor, 1967
-
(1967)
Ph.D. dissertation, Univ.
-
-
Reiter, R.1
-
42
-
-
0017538857
-
Petri nets
-
Sept
-
J. L. Peterson, “Petri nets,” Comput. Surv., vol. 9, no. 3, Sept. 1977
-
(1977)
Comput. Surv.
, vol.9
, Issue.3
-
-
Peterson, J.L.1
-
44
-
-
0018699409
-
Putting Petri nets to work
-
Dec
-
T. Agerwala, “Putting Petri nets to work,” Computer, vol. 1, no. 1, pp. 85–94, Dec. 1979
-
(1979)
Computer
, vol.1
, Issue.1
, pp. 85-94
-
-
Agerwala, T.1
-
45
-
-
0000223972
-
Parallel program schemata
-
May
-
R. M. Karp and R. E. Miller, “Parallel program schemata,” J. Comput. Syst. Sci., vol. 3, no. 2, pp. 147–195, May 1969
-
(1969)
J. Comput. Syst. Sci.
, vol.3
, Issue.2
, pp. 147-195
-
-
Karp, R.M.1
Miller, R.E.2
-
46
-
-
0023422785
-
Pipeline interleaved programmable DSP's: Parts I and II
-
Sept
-
E. A. Lee and D. G. Messerschmitt, “Pipeline interleaved programmable DSP’s: Parts I and II,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-35, pp. 1320–1333 and 1334–1345, Sept. 1987
-
(1987)
IEEE Trans. Acoust., Speech, Signal Processing
, vol.ASSP-35
, pp. 1320-1345
-
-
Lee, E.A.1
Messerschmitt, D.G.2
-
47
-
-
0023138886
-
Static scheduling of synchronous data flow programs for digital signal processing
-
Jan
-
E. A. Lee and D. G. Messerschmitt, “Static scheduling of synchronous data flow programs for digital signal processing,” IEEE Trans. Comput., vol. C-36, no. 2, pp. 24–35, Jan. 1987
-
(1987)
IEEE Trans. Comput.
, vol.C-36
, Issue.2
, pp. 24-35
-
-
Lee, E.A.1
Messerschmitt, D.G.2
-
49
-
-
0016313256
-
A comparison of list schedules for parallel processing systems
-
Dec
-
T. L. Adam, K. M. Chandy, and J. R. Dickson, “A comparison of list schedules for parallel processing systems,” Commun. Assoc. Comput. Mach., vol. 17, no. 12, pp. 685–690, Dec. 1974
-
(1974)
Commun. Assoc. Comput. Mach.
, vol.17
, Issue.12
, pp. 685-690
-
-
Adam, T.L.1
Chandy, K.M.2
Dickson, J.R.3
-
50
-
-
0001430010
-
Parallel sequencing and assembly line problems
-
T. C. Hu, “Parallel sequencing and assembly line problems,” Operations Res., vol. 9, no. 6, pp. 841-848,1961
-
(1961)
Operations Res.
, vol.9
, Issue.6
, pp. 841-848
-
-
Hu, T.C.1
-
51
-
-
0016657276
-
A preliminary evaluation of the critical path method for scheduling tasks on multiprocessor systems
-
Dec
-
W. H. Kohler, “A preliminary evaluation of the critical path method for scheduling tasks on multiprocessor systems,” IEEE Trans. Comput., vol. C-24, pp. 1235–1238, Dec. 1975
-
(1975)
IEEE Trans. Comput.
, vol.C-24
, pp. 1235-1238
-
-
Kohler, W.H.1
-
52
-
-
0022806218
-
A formal definition of data flow graph models
-
Nov
-
K. M. Kavi, B. P. Buckles, and U. N. Bhat, “A formal definition of data flow graph models,” IEEE Trans. Comput., vol. C-35, no. 11, pp. 940–948, Nov. 1986
-
(1986)
IEEE Trans. Comput.
, vol.C-35
, Issue.11
, pp. 940-948
-
-
Kavi, K.M.1
Buckles, B.P.2
Bhat, U.N.3
|