'Net-an' a full three-dimensional parasitic interconnect distributed RLC extractor for large full chip applications

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1995, Pages 495-498

  Akcasu, Osman Ersed ^a   Lu, Jesse ^a   Dalal, Alexander ^a   Mitra, Sundari ^a   Lev, Lavi ^a   Vasseghi, Nader ^a   Pance, Aleksandar ^a   Hingarh, Hem ^a   Basit, Haris ^a  

^a OEA Intl Inc ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; ELECTRIC FIELDS; ELECTRIC WIRING; EXTRACTION; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; THREE DIMENSIONAL; TIMING CIRCUITS; VLSI CIRCUITS;

DISTRIBUTED RLC EXTRACTOR; EXTRACTION CAPABILITY; REAL CLOCK DISTRIBUTION CIRCUITS;

COMPUTER SIMULATION;

EID: 0029520357     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)