A parallel multipole accelerated 3-D capacitance simulator based on an improved model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 12, 1996, Pages 1441-1450

  Wang, Zeyi ^a   Yuan, Yanhong ^a   Wu, Qiming ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY CONDITIONS; BOUNDARY ELEMENT METHOD; CAPACITANCE; COMPUTER SIMULATION; ELECTRIC CONDUCTORS; INTEGRAL EQUATIONS; LAPLACE TRANSFORMS; PARALLEL ALGORITHMS; PARALLEL PROCESSING SYSTEMS; SEMICONDUCTOR DEVICE MODELS; TRANSPUTERS;

BOUNDARY INTEGRAL EQUATIONS; PARASITIC CAPACITANCE; TRANSPUTER NETWORK;

VLSI CIRCUITS;

EID: 0030394807     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.552078     Document Type: Article

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