3D GIPER : Global Interconnect Parameter Extractor for Full-Chip Global Critical Path Analysis

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 615-618

  Oh, S Y ^a   Okasalu, K ^a   Moll, J ^a   Nakagawa, O S ^c   Rahmat, K ^a   Chang, N ^a   Hu, D ^b   Chow, J ^b   Young, T ^b   Ho, W ^b  

^a HEWLETT PACKARD LABORATORIES   (United States)

^b EPIC Design Technology Inc   (United States)

^c NONE

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT INTERCONNECTS; CAPACITANCE; CRITICAL PATH ANALYSIS; ELECTRIC FIELDS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; PARAMETER ESTIMATION; THREE DIMENSIONAL;

3-D NUMERICAL SIMULATION; FULL CHIPS; GLOBAL INTERCONNECTS; INTERCONNECT PARAMETER;

REGRESSION ANALYSIS; COMPUTER SIMULATION;

ELECTRIC FIELD DISTRIBUTION; FULL CHIP GLOBAL CRITICAL PATH ANALYSIS; GLOBAL INTERCONNECT PARAMETER EXTRACTOR;

EID: 0030393775     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554058     Document Type: Conference Paper

References (3)

1. O. E. AKcasu et a1,”NET-AN, A Full three-dimensional Parasibc Interconnect Distributed RLC Extractor for Large Full Chip Applications,” IEDM ‘95 pp.495-498.
2. ARCADIA Manual, EPIC
3. RAPHAEL Manual, TMA