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Volumn 5, Issue 1, 1986, Pages 215-220

Process-Based Three-Dimensional Capacitance Simulation—TRICEPS

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS - COMPUTER AIDED DESIGN;

EID: 0022562809     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1986.1270189     Document Type: Article
Times cited : (15)

References (12)
  • 1
    • 84939697568 scopus 로고
    • Practical versus theoretical limits of VLSI’s
    • ISSCC 1983 Panel, “Practical versus theoretical limits of VLSI’s,” in IEEE ISSCC Tech. Dig., pp. 211–212, 1983.
    • (1983) IEEE ISSCC Tech. Dig. , pp. 211-212
  • 2
    • 0020879241 scopus 로고    scopus 로고
    • Theoretical, practical, and analogical limits in ULSI
    • J. D. Meindl, “Theoretical, practical, and analogical limits in ULSI,” in IEEE IEDM, Tech. Dig., IEDM-83, pp. 8–13.
    • IEEE IEDM, Tech. Dig. , pp. 8-13
    • Meindl, J.D.1
  • 3
    • 0020779529 scopus 로고
    • Resistance extraction from mask layout data
    • M. Horowitz and R. W. Dutton, “Resistance extraction from mask layout data,” IEEE-CAD-2, no. 3, pp. 145–150, July 1983.
    • (1983) IEEE-CAD-2 , Issue.3 , pp. 145-150
    • Horowitz, M.1    Dutton, R.W.2
  • 4
    • 84939713088 scopus 로고
    • A 128-k word x 8 bit RAM
    • S. Suzuki et al., “A 128-k word x 8 bit RAM,” in IEEE ISSCC Tech. Dig., 1984, Pap. ISSCC-84, 106–107.
    • (1984) IEEE ISSCC Tech. Dig. , pp. 106-107
    • Suzuki, S.1
  • 5
    • 0019603042 scopus 로고
    • Coupting capacitances for two-dimensional wires
    • R. L. M. Dang and N. Shigyo, “Coupting capacitances for two-dimensional wires,” IEEE Electron Device Lett., vol. EDL-2, no. 8, pp. 196–197, 1981.
    • (1981) IEEE Electron Device Lett. , vol.EDL-2 , Issue.8 , pp. 196-197
    • Dang, R.L.M.1    Shigyo, N.2
  • 6
    • 0021640088 scopus 로고
    • Wiring capacitance simulation in two and three dimensions
    • M. Fukuma and R. H. Uebbing, “Wiring capacitance simulation in two and three dimensions,” in Dig. Tech. Pap. 1984 Symp. VLSI Tech., 1984, 24–25.
    • (1984) Dig. Tech. Pap. , pp. 24-25
    • Fukuma, M.1    Uebbing, R.H.2
  • 7
    • 0020244584 scopus 로고
    • Multidimensional simulation of VLSI wiring capacitance
    • P. E. Cotrell, E. M. Buturla, and D. R. Thomas, “Multidimensional simulation of VLSI wiring capacitance,” in IEDM 82 Tech. Dig., 1982 Pap. IEEE IEDM-82, pp. 548–551.
    • (1982) IEDM 82 Tech. Dig. , pp. 548-551
    • Cotrell, P.E.1    Buturla, E.M.2    Thomas, D.R.3
  • 11
    • 0015626349 scopus 로고
    • A two-dimensional mathematical model of the insulated-gate field-effect transistor
    • M. S. Mock, “A two-dimensional mathematical model of the insulated-gate field-effect transistor,” Solid-State Electron., vol. 16, pp. 601–609, 1973.
    • (1973) Solid-State Electron. , vol.16 , pp. 601-609
    • Mock, M.S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.