Time-Domain Macromodels for VLSI Interconnect Analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 10, 1994, Pages 1257-1270

  Kim, Seok Yoon ^a   Gopal, Nanda ^a   Pillage, Lawrence T ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK PARAMETERS; ELECTRIC WAVEFORMS; ELECTRIC WIRING; SEMICONDUCTOR DEVICE STRUCTURES; TIME DOMAIN ANALYSIS; VLSI CIRCUITS;

ASYMPTOTIC WAVEFORM EVALUATION; INTERCONNECT PARASITICS; TIME DOMAIN MACROMODELS; VLSI INTERCONNECT ANALYSIS;

SEMICONDUCTOR DEVICE MODELS;

EID: 0028517129     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.317469     Document Type: Article

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