A channel resistance derivative method for effective channel length extraction in LDD MOSFET’s

IEEE Transactions on Electron Devices

Volumn 47, Issue 3, 2000, Pages 648-650

  Niu, Guofu ^a   Cressler, John D ^a   Mathew, Suraj J ^a   Subbanna, Seshu ^b  

^a AUBURN UNIVERSITY   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

Effective channel length; MOSFET; Parameter extraction; Source drain resistance

Indexed keywords

ELECTRIC RESISTANCE; GATES (TRANSISTOR);

CHANNEL RESISTANCE DERIVATIVE METHODS;

MOSFET DEVICES;

EID: 0033892201     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.824743     Document Type: Article

References (12)

1. K. Terada and H. Muta, "A new method to determine effective MOSFET channel length," Jpn. J. Appl. Phys.. vol. 18, p. 953, 1979.
2. K. K. Ng and J. R. Brews, "Measuring the effective channel length of MOSFET s "IEEE Circuits Devices Mag., vol. 6, pp. 33-38, Nov. 1990.
3. Y. Taur et al, "A new 'shift-and-ratio' method for MOSFET channel length extraction," IEEE Electron Device Lett., vol. 13, pp. 267-269, 1992.
4. S. Biesemans, M. Hendriks, S. Kubicek, and K. D. Meyer, "Practical accuracy analysis of some existing effective channel length and series resistance extraction method for MOSFET's," IEEE Trans. Electron Devices, vol. 45, pp. 1310-1316, 1998.
5. J. C. Sun, M. R. Wordeman, and S. E. Eaux, "On the accuracy of channel length characterization of EDD MOSFET," IEEE Trans. Electron Devices, vol. 43, p. 580, 1996.
6. K. Takeuchi, N. Kasai, T. Kunio, and K. Terada, "An effective channel length determination method for EDD MOSFET's," IEEE Trans. Electron Devices, vol. 43, pp. 580-587, Apr. 1996.
7. D. C. Ahlgren et al, "Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplace," in 1EDM Tech. Dig., 1996, pp. 859-862.
8. D. Esseni et al, "Nonscaling of MOSFET's linear resistance in the deep submicrometer regime," IEEE Electron Device Lett., vol. 19, pp. 131-133, 1998.
9. G. J. Hu, C. Chang, and Y. Chia, "Gate-voltage-dependent effective channel length and series resistance of EDD MOSFET's," IEEE Trans. Electron Devices, Vol. ED34, p. 2469, 1987.
10. P. DeWolf et al, "Direct measurement of Lrrr and channel profile in MOSFET's using 2-D carrier profiling techniques," in IEDM Tech. Dig., Dec. 1998, pp. 559-562.
11. W. Timp, M. O'Malley, R. Kleiman, and J. Carno, "Two-dimensional dopant profiling of a 60 nm gate length nMOSFET using scanning capacitance microscopy," in IEDM Tech. Dig., Dec. 1998, pp. 555-559.
12. G. F. Niu, J. D. Cressler, S. J. Mathew, and S. Subbanna, "A total resistance slope-based effective channel mobility extraction method for deep submicron CMOS technology," IEEE Trans. Electron Devices, vol. 46, pp. 1912-1914, 1999.