Design techniques for a low-power low-cost CMOS A/D converter

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 8, 1998, Pages 1244-1248

  Chang, Dong Young ^a,b   Lee, Seung Hoon ^a  

^a Sogang University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

Algorithmic analog to digital converter; Metal to metal capacitor; Poly layer lines; Power reduction; Switched bias

Indexed keywords

ALGORITHMS; CAPACITORS; CMOS INTEGRATED CIRCUITS; DESIGN; DIGITAL INTEGRATED CIRCUITS; PERFORMANCE; SIGNAL TO NOISE RATIO;

METAL TO METAL CAPACITORS;

ANALOG TO DIGITAL CONVERSION;

EID: 0032136627     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.705363     Document Type: Article

References (17)

1. D. W. Cline and P. R. Gray, "A power optimized 13-bit 5Msample/s pipelined analog to digital converter in 1.2 μm CMOS," in Proc. Custom Integrated Circuits Conf., May 1995, pp. 219-222.
2. K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger, "A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers," IEEE J. Solid-State Circuits, vol. 32, pp. 312-320, Mar. 1997.
3. P. C. Yu and H. S. Lee, "A 2.5-V, 12-b, 5-Msample/s pipeline CMOS ADC," IEEE J. Solid-State Circuits, vol. 31, pp. 1854-1861, Dec. 1996.
4. G. C. Ahn, H. C. Choi, S. I. Lim, S. H. Lee, and C. D Lee, "A 12-b, 10-MHz, 250-mW CMOS A/D converter," IEEE J. Solid-State Circuits, vol. 31, pp. 2030-2035, Dec. 1996.
5. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. New York: Wiley, 1993.
6. 2," IEEE Electron Device Lett., vol. EDL-7, pp. 446-448, July 1986.
7. R. Moazzami, J. C. Lee, and C. Hu, "Temperature acceleration of time-dependent dielectric breakdown," IEEE Trans. Electron Devices, vol. 36, pp. 2462-2465, Nov. 1989.
8. 2 at very low voltages," IEEE Trans. Electron Devices, vol. 41, pp. 1227-1232, July 1994.
9. bd): A physical-damage model of dielectric breakdown," IEEE Trans. Electron Devices, vol. 41, pp. 1595-1602, Sept. 1994.
10. S. Ma, J. P. McVitte, and K. C. Saraswat, "Effects of wafer temperature on plasma charging induced damage to MOS gate oxide," IEEE Electron Device Lett., vol. 16, pp. 534-536, Dec. 1995.
11. R. Tu, J. C. King, H. Shin, and C. Hu, "Simulating process-induced gate oxide damage in circuits," IEEE Trans. Electron Devices, vol. 44, pp. 1393-1400, Sept. 1997.
12. J. T. Wu and B. Wooley, "A 100-MHz pipelined CMOS comparator," IEEE J. Solid-State Circuits, vol. 23, pp. 1379-1385, Dec. 1988.
13. P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, "A ratio-independent algorithmic analog-to-digital conversion technique," IEEE J. Solid-State Circuits, vol. SC-19, pp. 827-836, Dec. 1984.
14. H. Ohara, H. X. Ngo, M. J. Armstrong, C. F. Rahim, and P. R. Gray, "A CMOS programmable self-calibrating 13-bit eight-channel data acquisiton peripheral," IEEE J. Solid-State Circuits, vol. SC-22, pp. 930-938, Dec. 1987.
15. K. Nagaraj, "Efficient circuit configuration for algorithmic analog to digital converters," IEEE Trans. Circuits Syst. II, vol. 40, pp. 777-785, Dec. 1993.
16. A. Kitagawa, M. Kokubo, T. Tsukada, T. Matsuura, M. Hotta, K. Maiso, E. Yamamoto, and E. Imaizumi, "A 10b 3Msample/s CMOS cyclic ADC," in IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 1995, pp. 314-315.
17. S. H. Lee and B. S. Song, "Digital-domain calibration of multistep analog-to-digital converters," IEEE J. Solid-State Circuits, vol. 27, pp. 1679-1688, Dec. 1992.